Semiconductor device and method of fabricating thereof capable of reducing a shallow trench isolation stress influence by utilizing layout pattern designs
View Patent ↗Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate, a plurality of contact metals, and a gate electrode. The semiconductor substrate has an active region and a dummy active region, and a plurality of contact metals are formed in the active region. A gate electrode is located between the contact metals in the active region. A first distance between the active region and the dummy active region, and a second distance between an edge of the contact metal and an edge of the active region are set such that a channel characteristic of the active region is improved.
1. A semiconductor device comprising:
a semiconductor substrate having an active region and a dummy active region;
a plurality of contact metals formed in the active region; and
a gate electrode located between the contact metals in the active region, wherein a first distance between the active region and the dummy active region, and a second distance between an edge of the contact metal and an edge of the active region are set such that a channel characteristic of the active region improves.
2. The semiconductor device according to claim 1 , wherein the channel characteristic of the active region increases impurity diffusion and carrier mobility.
3. The semiconductor device according to claim 1 , wherein the first distance is in a range of 0.7-2.6 μm, and the second distance is in a range of 0.15-2.6 μm.
4. The semiconductor device according to claim 1 , wherein the first distance between the active region and the dummy active region is 0.7 μm, and the second distance between an edge of the contact metal and an edge of the active region is in a range of 0.15-0.95 μm.
5. The semiconductor device according to claim 1 , wherein the first distance between the active region and the dummy active region is 2.6 μm, and the second distance between an edge of the contact metal and an edge of the active region is in a range of 0.15-0.95 μm.
6. The semiconductor device according to claim 1 , wherein a threshold voltage and a drain saturation current of a transistor realized in the active region are controlled by controlling the first and second distances.
7. The semiconductor device according to claim 1 , wherein a gain and a drain saturation current of a transistor realized in the active region are controlled depending on existence of the dummy active region.
8. A semiconductor device comprising:
an active region formed on a semiconductor substrate;
source/drain regions formed in an edge of the active region;
a gate electrode formed across a central portion of the active region; and
a plurality of dummy gate electrodes arranged on both sides of the gate electrode, wherein a width of the active region is adjusted to a predetermined distance such that a channel characteristic of the active region improves, wherein the plurality of dummy gate electrodes are arranged on both sides of the gate electrode such that the dummy gate electrodes are overlapping with electrodes of the source/drain regions.
9. The semiconductor device according to claim 8 , wherein the width of the active region is in a range of 0.07-4.66 μm.