Method for manufacturing semiconductor device

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate trench in a semiconductor substrate;

forming a gate insulation film in an inner wall of the gate trench;

filling a gate electrode material into at least an inside of the gate trench;

selectively forming a punch-through stopper region, using a mask in a prescribed position of the semiconductor substrate that is adjacent to the gate trench;

forming a first source/drain region above the punch-through stopper region using the mask used to form the punch-through stopper region;

forming a gate electrode by patterning the gate electrode material subsequent to forming the punch-through stopper region and the first source/drain region; and

forming a second source/drain region which has different impurity concentration from the first source/drain region on an opposite side from the first source/drain region as viewed from the gate trench subsequent to patterning the gate electrode material.

2. The method for manufacturing a semiconductor device as claimed in claim 1 , wherein the step for forming a punch-through stopper region is performed subsequent to the step for filling the gate electrode material into a gate trench.

3. The method for manufacturing a semiconductor device as claimed in claim 1 , wherein the step for forming a punch-through stopper region is performed prior to the step for forming a gate trench.

4. The method for manufacturing a semiconductor device as claimed in claim 3 , wherein the first source/drain region has a higher impurity concentration than the second source/drain region.

5. The method for manufacturing a semiconductor device as claimed in claim 4 , wherein the first source/drain region is connected to a bit line, and the second source/drain region is connected to a cell capacitor.

6. The method for manufacturing a semiconductor device as claimed in claim 5 , wherein the gate electrode material comprises a multilayer film in the step for filling the gate electrode material into a gate trench.

7. The method for manufacturing a semiconductor device as claimed in claim 6 , wherein the multilayer film comprises a first conducting film formed in at least the gate trench; and a second conducting film formed above the gate trench.

8. The method for manufacturing a semiconductor device as claimed in claim 7 , wherein

the first conducting film is a silicon film; and

the second conducting film is a metal film or a refractory metal suicide film.

9. A method for manufacturing a semiconductor device, comprising:

a first step for forming first and second gate trenches in a semiconductor substrate;

a second step for forming a gate insulation film on inner wall surfaces of the first and second gate trenches;

a third step for filling a gate electrode material into at least the first and second gate trenches;

a fourth step for forming a mask that has an opening for exposing an area between a region where the first gate trench is formed and a region where the second gate trench is formed;

a fifth step for selectively forming a punch-through stopper region by ion implantation of a first conductive impurity into the semiconductor substrate under the opening using the mask;

a sixth step for selectively forming a first source/drain region that is shallower than the punch-through stopper region by ion implantation of a second conductive impurity into the semiconductor substrate under the opening using the mask;

a seventh step for forming a gate electrode by pattering the gate electrode material; and

an eighth step for selectively forming a second source/drain region by ion implantation of the second conductive impurity which has a lower impurity concentration than the first source/drain region, in a region on an opposite side from the first source/drain region as viewed from the first gate trench, and a region on an opposite side from the first source/drain region as viewed from the second gate trench; wherein

the fourth through sixth steps are performed prior to the seventh step, and

the eighth step is performed subsequent to the seventh step.

10. The method for manufacturing a semiconductor device as claimed in claim 9 , wherein the fifth through seventh steps are performed subsequent to the third step.

11. The method for manufacturing a semiconductor device as claimed in claim 9 , wherein the fifth through seventh steps are performed prior to the first step.

12. The method for manufacturing a semiconductor device as claimed in claim 11 , wherein the opening of the mask also exposes a portion of the first and second gate trenches.

13. The method for manufacturing a semiconductor device as claimed in claim 12 , wherein

the gate electrode material comprises a multilayer film in which first and second conducting films are layered in sequence;

the first conducting film is a silicon film; and

the second conducting film is a metal film or a refractory metal silicide film.

14. The method for manufacturing a semiconductor device as claimed in claim 13 , wherein

the first source/drain region is connected to a bit line; and

the second source/drain region is connected to a cell capacitor.

15. A method of manufacturing a semiconductor device comprising:

selectively forming an isolation region in a semiconductor layer to define an element formation region of one conductivity type, the element formation region having first, second and third portions, the second portion being sandwiched between the first and third portions;

forming a punch-through stopper region of the one conductivity type and one of source and drain regions of the other conductivity type in the first portion of the element formation region;

forming the other of the source and drain regions of the other conductivity type in the third portion of the element formation region;

removing the second portion to form a trench between the first and third portions of the element formation region;

filling the trench with a gate material layer with an intervention of a gate insulating film therebetween, the gate material layer being elongated over the element formation region; and

patterning the gate material layer to form a gate electrode, wherein

the patterning the gate material layer is carried out between the forming a punch-through stopper region of the one conductivity type and one of source and drain regions of the other conductivity type, and the forming the other of the source and drain regions of the other conductivity type.

16. The method as claimed in claim 15 , wherein the filling the trench with a gate material layer is carried out before the forming a punch-through stopper region of the one conductivity type and one of source and drain regions of the other conductivity type.

17. The method as claimed in claim 16 , wherein the punch-through stopper region of the one conductivity type is formed before forming the one of source and drain regions of the other conductivity type doping.

18. The method as claimed in claim 15 , wherein the removing the second portion to form a trench is carried out before the forming a punch-through stopper region of the one conductivity type and one of source and drain regions of the other conductivity type.

19. The method as claimed in claim 18 , wherein the punch-through stopper region of the one conductivity type is formed before forming the one of source and drain regions of the other conductivity type doping.