Electrostatic discharge protected circuits

1. A method for designing an electrostatic discharge (ESD) protected analog circuit, comprising:

creating an original analog circuit design comprising a plurality of interconnected functional components and circuit-level ESD protection components with predetermined electric properties for achieving a predetermined analog performance during normal operation of the original circuit and a predetermined ESD robustness during an ESD event on the original circuit;

simulating at least one ESD event on the original analog circuit design to identify at least one weak spot in the original circuit; and

adding at least one component-level ESD protection component to a node between at least two functional components of the original analog circuit design to shunt ESD current around the at least one weak spot to reduce failure of the weak spot during an ESD event.

2. The method according to claim 1 , wherein the component-level ESD protection components have substantially no influence on the analog performance during normal operation due to their size.

3. The method according to claim 1 , further comprising evaluating the electric properties of the circuit-level ESD protection components.

4. The method of claim 3 , further comprising adapting the circuit-level ESD protection components to reduce their impact on the analog performance during normal operation based on the evaluation.

5. The method according to claim 1 , wherein the component-level ESD protection components comprise a diode network that is added to protect a functional element at the identified weak spot from an ESD event.

6. The method according to claim 5 , wherein the diode network comprises diodes of contact size.

7. The method according to claim 1 , wherein the circuit-level ESD protection components are plug&play ESD protection components and wherein creating an analog circuit design includes:

creating the analog circuit design comprising the plurality of interconnected functional components and determining their electric properties for achieving the predetermined analog performance during normal operation of the circuit; and

adding the plug&play ESD protection components onto the analog circuit design and determining their electric properties for achieving the predetermined ESD robustness during an ESD event on the circuit.

8. The method according to claim 1 , wherein creating an analog circuit design includes co-designing the circuit-level ESD protection components with the functional components.

9. A method according to claim 1 , wherein:

the weak spot functional component is a transistor with a gate, a source, and a drain; and

the component-level ESD protection includes a diode network between the gate and the drain.

10. A method according to claim 1 , wherein the steps of simulating and adding are performed iteratively to identify successive weak spots and to add corresponding component-level ESD protection components.

11. An analog circuit, comprising in combination:

a plurality of interconnected functional components with predetermined electric properties for achieving a predetermined analog performance during normal operation of the circuit;

a plurality of circuit-level electrostatic discharge (ESD) protection components connected to the functional components with predetermined electric properties for achieving a predetermined ESD robustness during an ESD event on the circuit; and

at least one component-level ESD protection component connected to a node between at least two of the functional components to shunt ESD current around a component that has been identified as a weak spot in the circuit to reduce failure of the weak spot during an ESD event.

12. The analog circuit according to claim 11 , wherein the at least one component-level ESD protection component comprises a protective diode network that is adapted for protecting the at least one functional component identified as the weak spot during the ESD event.

13. The analog circuit according to claim 12 , wherein the diode network comprises diodes of contact size.

14. The analog circuit according to claim 11 , wherein the circuit is a low noise amplifier circuit for RF signals comprising:

a first transistor having a source, a drain, a gate, and a gate oxide separating the gate from the source and the drain, wherein the first transistor forms one of the functional components of the circuit,

first component-level ESD protection components connecting the gate to the drain and second component-level ESD protection components connecting the gate to ground, wherein the first and second ESD protection components are provided to avoid breakdown of the gate oxide during an ESD event.

15. The analog circuit according to claim 14 , wherein the first and second ESD protection components comprise voltage clamping devices for clamping a voltage over the gate oxide during the ESD event at a predetermined maximum below a breakdown voltage of the gate oxide.

16. The analog circuit according to claim 15 , wherein the first ESD protection components comprise an array of diodes arranged in series.

17. The analog circuit according to claim 16 , wherein the diodes are of contact size.

18. The analog circuit according to claim 15 , wherein the second ESD protection components comprise an array of diodes arranged in parallel and in opposite directions.

19. The analog circuit according to claim 18 , wherein the diodes are of contact size.

20. The analog circuit according to claim 14 , further comprising third and fourth ESD protection components that form low-impedance paths towards ground at frequencies below that of RF signals for which the low noise amplifier is designed.

21. The analog circuit according to claim 20 , wherein the third and fourth ESD protection components comprise inductors at an input and an output of the circuit.

22. The analog circuit according to claim 11 , wherein the circuit is a distributed amplifier comprising:

a plurality of parallel gain stages, each comprising at least one transistor as one of the functional components, each transistor having a source, a drain, a gate, and a gate oxide separating the gate from the source and the drain,

a network of the circuit-level ESD protection components distributed over the gain stages for shunting ESD currents upon occurrence of ESD events to ground, and

first and second component-level ESD protection components associated with each of the gain stages, the first component-level ESD protection components connecting the gate to the drain and the second component-level ESD protection components connecting the gate to ground, wherein the first and second ESD protection components are provided to avoid breakdown of the gate oxide during an ESD event.

23. The analog circuit according to claim 22 , wherein the first and second ESD protection components comprise voltage clamping devices for clamping a voltage over the gate oxide during the ESD event at a predetermined maximum below a breakdown voltage of the gate oxide.

24. The analog circuit according to claim 23 , wherein the first ESD protection components comprise an array of diodes arranged in series.

25. The analog circuit according to claim 24 , wherein the diodes are of contact size.

26. The analog circuit according to claim 23 , wherein the second ESD protection components comprise an array of diodes arranged in parallel and in opposite directions.

27. The analog circuit according to claim 26 , wherein the diodes are of contact size.

28. An analog circuit according to claim 11 , wherein:

the weak spot functional component is a transistor with a gate, a source, and a drain; and

the component-level ESD protection includes a diode network between the gate and the drain.