Epitaxially coated silicon wafer and method for producing epitaxially coated silicon wafers
View Patent ↗Epitaxially coated silicon wafers, are produced by epitaxially coating a multiplicity of wafers polished at least on their front sides, successively and individually in an epitaxy reactor, by placing a silicon wafer on a susceptor, pretreating under a hydrogen atmosphere followed by addition of an etching medium to the hydrogen atmosphere, coating epitaxially on the polished front side and removing the water from the epitaxy reactor. The susceptor is then heated, in each case, to a temperature of at least 1000° C. under a hydrogen atmosphere, and furthermore an etching treatment of the susceptor and a momentary coating of the susceptor with silicon are effected after a specific number of epitaxial coatings. Silicon wafers characterized by a parameter R30-1 mm of −10 nm to +10 nm, determined at a distance of 1 mm from the edge of the silicon wafer are produced.
1. A method for producing epitaxially coated silicon wafers, in which a multiplicity of silicon wafers which are polished at least on their front sides are provided and successively and individually coated in an epitaxy reactor, comprising:
placing one of the silicon wafers on a susceptor in the epitaxy reactor, pretreating the wafer under a hydrogen atmosphere in a first step, adding an etching medium to the hydrogen atmosphere in a second step, subsequently epitaxially coating the wafer on its polished front side, and removing the wafer from the epitaxy reactor, and afterwards heating the susceptor to a temperature of at least 1000° C. under a hydrogen atmosphere, and after a specific number of epitaxial coatings etching the susceptor followed by a momentary coating of the susceptor with silicon
wherein the silicon wafer is characterized by a parameter R30 -1 mm of −10 nm to +10 nm, corresponding to a deviation, at a distance of 1 mm from the edge of the silicon wafer, of an average thickness cross section with respect to a reference line determined by regression.
2. The method of claim 1 , wherein the treatment in a hydrogen atmosphere is effected at a hydrogen flow rate of 0-100 slm for a duration of up to 120 s.
3. The method of claim 2 , wherein the treatment in the hydrogen atmosphere is effected at a hydrogen flow rate of 30-60 slm.
4. The method of claim 1 , wherein the pretreatment with addition of etching medium into the hydrogen atmosphere is effected at a hydrogen flow rate of 0-100 slm for a duration of up to 120 s.
5. The method of claim 4 , wherein the pretreatment with addition of an etching medium into the hydrogen atmosphere is effected at a hydrogen flow rate of 30-60 slm.
6. The method of claim 1 , wherein the susceptor is heated to a temperature of at least 1100° C.
7. The method of claim 1 , wherein the susceptor, after being heated to a temperature, is kept at that temperature for 5-15 s.
8. The method of claim 1 , wherein trichlorosilane is used as a source gas during the epitaxial coating at a deposition temperature of 1050-1150° C.
9. The method of claim 1 , wherein hydrogen chloride is used as the etching medium during the treatment of the susceptor and during pretreatment of the silicon wafer.
10. The method of claim 1 , wherein the silicon wafers provided are wafers of monocrystalline silicon, SOI wafers, wafers having a strained silicon layer, or sSOI wafers.
11. A silicon wafer having a front side and a rear side, at least the front side being polished and having an epitaxial layer on its front side, characterized by a parameter R30-1 mm of −10 nm to +10 nm, corresponding to a deviation, at a distance of 1 mm from the edge of the silicon wafer, of an average thickness cross section with respect to a reference line determined by regression.
12. The silicon wafer of claim 11 , having a parameter R30-1 mm of −5 nm to +5 nm.
13. The silicon wafer of claim 11 , wherein the epitaxial layer has a thickness of 0.5 to 5 μm.
14. The silicon wafer of claim 11 , wherein the silicon wafer is a wafer made of monocrystalline silicon, an SOI wafer, a wafer having a strained silicon layer, or an sSOI wafer with an epitaxial coating.