Method for manufacturing vertical structure light emitting diode

1. A method for manufacturing a vertical light emitting diode comprising steps of:

forming a light emitting structure having an n-type clad layer, an active layer and a p-type clad layer sequentially formed therein on a growth substrate having a plurality of device areas and at least one device isolation area;

forming corresponding p-type electrodes on the light emitting structure on the device areas;

providing a glass substrate having through holes perforated therein on the p-electrodes so that the through holes are disposed corresponding to the p-electrodes;

plating the through holes with a metal material to form patterns of a plating layer on the p-electrodes;

removing the growth substrate to form n-electrodes on the n-type clad layer; and

removing the glass substrate via etching.

2. The method according to claim 1 , wherein the step of providing the glass substrate on the p-electrodes comprises: bonding the glass substrate having the through holes perforated therein onto the p-electrodes.

3. The method according to claim 1 , wherein the step of providing the glass substrate on the p-electrodes comprises:

bonding the glass substrate onto the p-electrodes;

perforating the through holes in the glass substrate so that the through holes are disposed corresponding to the p-electrodes.

4. The method according to claim 1 , further comprising: between the step of forming the light emitting structure and forming the p-electrodes, forming a trench in the light emitting structure on the device isolation area to separate the light emitting structure into individual device areas.

5. The method according to claim 1 , further comprising: after forming the p-electrodes, forming a trench in the light emitting structure on the device isolation area to separate the light emitting structure into individual device areas.

6. The method according to claim 1 , wherein the plating layer comprises one selected from a group consisting of Au, Cu, Ni, Ag, Cr, W, Al, Pt, Sn, Pb, Fe, Ti, Mo, and alloys thereof.

7. The method according to claim 1 , further comprising: before forming the patterns of the plating layer, forming a plating seed layer on the p-electrodes.

8. The method according to claim 1 , wherein the plating seed layer is formed via electro less plating or deposition.

9. The method according to claim 1 , wherein the step of removing the growth substrate is carried out by one selected from a group consisting of physical, chemical and mechanical methods.

10. The method according to claim 9 , wherein the growth substrate is removed by laser lift-off.

11. The method according to claim 1 , wherein the n-type clad layer, the active layer and the p-type clad layer are made of a group III-V compound semiconductor material.

12. The method according to claim 1 , wherein the p-type clad layer, the active layer and the p-type clad layer are made of a semiconductor material having a composition expressed by Al x Ga y In (1-x-y) P, where 0≦x≦1, 0y≦1, 0≦x+y≦1.

13. The method according to claim 12 , wherein the growth substrate comprises a sapphire substrate.

14. The method according to claim 1 , wherein the n-type clad layer, the active layer and the p-type clad layer are made of a semiconductor material having a composition expressed by Al x Ga y In (1-x-y) P, where 0≦x≦1, 0≦y≦1, 0≦x+y≦1.

15. The method according to claim 1 , wherein the n-type clad layer, the active layer and the p-type clad layer are made of a semiconductor material having a composition expressed by Al x Ga 1-x As, where 0≦x≦1.