Semiconductor device and method for designing same
View Patent ↗A silica residue is generated, due to a presence of a step formed by a presence of the first layer metallic interconnect, and then, the residual silica is etched to form hollow portions when vias for the metallic interconnect provided in a layer above thereof is formed, and further, insulating materials remained above the hollow portions flakes off to create contaminants, leading to a reduction in the production yield. In the present invention, interconnects provided in a layer underlying a via group, which are provided for coupling to the upper layer interconnect layer, are disposed so as to cover vias composing its via group.
1. A semiconductor device, comprising:
a first metallic interconnect;
a second metallic interconnect provided on said first metallic interconnect;
a third metallic interconnect provided on said second metallic interconnect; and
a plurality of vias for coupling said second metallic interconnect to said third metallic interconnect,
wherein said first metallic interconnect is provided so as to overlap with all of said plurality of vias;
wherein said first metallic interconnect extends in a first direction so as to overlap with some of said plurality of vias, said second metallic interconnect and said third metallic interconnect extend in a second direction that is perpendicular to said first direction, wherein the first metallic interconnect has a protruding portion that protrudes from said first metallic interconnect toward said second direction, and the rest of said plurality of vias overlap with the protruding portion.
2. The semiconductor device according to claim 1 , wherein a first power supply potential is supplied to said first metallic interconnect, and a power supply potential, which is different from said first power supply potential, is supplied to said second metallic interconnect.
3. The semiconductor device of claim 1 , further comprising a planarized interlayer insulating film sandwiched between the second and third metallic interconnects in which the plurality of vias are formed, the planarized interlayer insulating film comprising a plasma oxide film coated with silica.
4. A semiconductor device, comprising:
a first metallic interconnect;
a second metallic interconnect provided on said first metallic interconnect;
a third metallic interconnect provided on said second metallic interconnect; and
a plurality of vias for coupling said second metallic interconnect to said third metallic interconnect,
wherein said first metallic interconnect comprises a functional portion and an extension portion, wherein the functional portion is a portion sufficient to carry out the interconnect function of the first metallic interconnect and the extension portion extends from and perpendicular to the functional portion so as to overlap with at least some of said plurality of vias, such that the functional and extension portions of the first metallic interconnect overlap all of the plurality of vias.
5. The semiconductor device of claim 4 , further comprising a planarized interlayer insulating film sandwiched between the second and third metallic interconnects in which the plurality of vias are formed, the planarized interlayer insulating film comprising a plasma oxide film coated with silica.