Output control signal generating circuit
View Patent ↗An output control signal generating circuit includes latch circuits that are connected in cascade, and a timing signal generating circuit that generates a timing signal to be supplied to the latch circuits, based on a second clock of which phase is advanced from the phase of a first clock used to take in a read command. The timing signal generating circuit delays the phase of a timing signal to be supplied to a relatively pre-stage latch circuit included in the latch circuits, from the phase of a timing signal to be supplied to a relatively latter stage latch circuit included in the latch circuits. With this arrangement, a latch margin of a first latch circuit does not depend on the cycle of an external clock. Accordingly, even when a clock has a very high speed, the output can be controlled correctly.
1. An output control signal generating circuit that takes in a read command in synchronism with a first clock and that controls an output timing of read data in synchronism with the first clock after n (where n is a natural number) cycles, the output control signal generating circuit comprising:
n latch circuits connected in cascade, including a first-stage latch circuit that latches an internal command generated based on the read command and a last-stage latch circuit that outputs an output control signal; and
a timing signal generating circuit that generates a timing signal to be supplied to the n latch circuits, based on a second clock of which phase is advanced from a phase of the first clock, wherein
the timing signal generating circuit delays the phase of a timing signal to be supplied to a relatively pre-stage latch circuit included in the latch circuits, from the phase of a timing signal to be supplied to a relatively latter stage latch circuit included in the latch circuits.
2. The output control signal generating circuit as claimed in claim 1 , wherein the first-stage latch circuit latches the internal command in synchronism with a timing signal corresponding to an active edge of the first clock used to take in the read command.
3. The output control signal generating circuit as claimed in claim 2 , wherein a k-th (where k is a natural number equal to or smaller than n) latch circuit counted from the first-stage latch circuit operates in synchronism with a timing signal generated based on a k-th active edge, from the viewpoint of the active edge of the first clock used to take in the read command.
4. The output control signal generating circuit as claimed in claim 1 , wherein the first clock is an external clock, and the second clock is an internal clock.
5. The output control signal generating circuit as claimed in claim 1 , wherein the timing signal generating circuit includes n delay circuits that are connected in cascade.
6. The output control signal generating circuit as claimed in claim 5 , wherein the timing signal generating circuit supplies a timing signal delayed by (n−k+1) delay elements, to a k-th (where k is a natural number equal to or smaller than n) latch circuit counted from the first latch circuit.
7. The output control signal generating circuit as claimed in claim 5 , wherein delays of the timing signal performed by the n delay circuits are substantially equal to each other.