Progressive random access scan circuitry
A scan cell is described for testing an integrated circuit. The scan cell may include circuitry adapted to operate in a non-test mode as a storage element and adapted to operate as a static random access memory (SRAM) cell in a test mode. For example, the circuitry may include one or more pass transistors and a flip flop. The scan cell may be one of a plurality of addressable scan cells in one or more grids for testing the integrated circuit. For example, the scan cells may be arranged in a single grid or may be partitioned into two or more grids. The scan cell may be used for reliability testing or for performance testing. The PRAS cell for performance testing may be staged, with a first pattern applied and then a second pattern applied. For example, one section of the scan cell may operate using a clock cycle of Φ 1 and another section of the PRAS cell may operate using a clock cycle of Φ 2 which is different from Φ 1 .
1. A scan cell for testing an integrated circuit, the scan cell operating in a test mode and a non-test mode, the scan cell comprising:
circuitry configured to receive an input signal indicative of being in a test mode or a non-test mode,
wherein the circuitry is configured to activate a storage element in order to operate in the non-test mode as a storage element when the input signal is indicative of the non-test mode, and
wherein the circuitry is configured to activate a feedback group of at least two inverters accessed by one or more data lines, and one or more pass transistors in order to operate as a static random access memory (SRAM) cell in the test mode when the input signal is indicative of the test mode.
2. The scan cell of claim 1 , wherein the circuitry comprises a storage element and at least one pass transistor.
3. The scan cell of claim 2 , wherein the circuitry consists of the storage element and one or more pass transistors.
4. The scan cell of claim 3 , wherein the storage element comprises a flip flop.
5. The scan cell of claim 3 , wherein the scan cell is addressable.
6. The scan cell of claim 5 , wherein the one or more pass transistors are controlled by at least one address line for addressing the scan cell.
7. The scan cell of claim 6 , wherein the at least one address line comprises a first address line and a second address line; and
wherein the first address line is connected to a gate of the one or more pass transistors; and
wherein the second address line is in communication with one of a source or drain of the one or more pass transistors.
8. The scan cell of claim 7 , wherein the first address line comprises a row enable line and the second address line comprises a column enable line.
9. The scan cell of claim 7 , wherein a data line is connected to an input of driver circuitry controlled by the second address line, an output of the driver being connected to the source or drain of the one or more pass transistors.
10. A scan cell for testing an integrated circuit, the scan cell operating in a test mode and a non-test mode, the scan cell comprising:
a storage element having an input and an output;
clock circuitry in communication with the storage element; and
two or fewer pass transistors, at least a part of each of the pass transistors electrically connected with at least a part of the storage element, the pass transistors being used to individually address the scan cell during the test mode.
11. The scan cell of claim 10 , wherein the storage element comprises a flip flop with a master stage and a slave stage; and
wherein each of the two pass transistors are electrically connected to the master stage of the flip flop.
12. The scan cell of claim 10 , wherein a critical path is defined by signal flow through the scan cell in a non-test mode; and
wherein the two pass transistors are in a path outside of the critical path.
13. A scan cell for testing an integrated circuit, the scan cell operating in a test mode and a non-test mode, the scan cell comprising:
a storage element having an input and an output;
one or more pass transistors, at least a part of each of the pass transistors electrically connected with at least a part of the storage element, the pass transistors being used to individually address the scan cell during the test mode; and
at least one input line for the scan cell, the at least one input line being used to input data to the storage element in the scan cell and being used to address the scan cell.
14. The scan cell of claim 13 , wherein at least one of the address lines is electrically connected to the one or more pass transistors to turn the one or more pass transistors on and off.
15. The scan cell of claim 14 , wherein at least one driver is in communication with the scan cell, the driver comprising an input line, an output line, and a control line;
wherein another of the address lines comprises the control line for the driver;
wherein an input data line comprises the input line for the driver; and
wherein the output line of the driver comprises the at least one input line for the scan cell.
16. The scan cell of claim 15 , wherein the output line for the driver is electrically connected to one of a source or drain of the pass transistor; and
wherein another of the source or drain of the pass transistor is electrically connected to the storage element.
17. A scan cell for testing an integrated circuit, the scan cell operating in a test mode and a non-test mode, the scan cell comprising:
a storage element having at least a first stage and a second stage, the first stage operating on a first clock cycle (Φ 1 ) and the second stage operating on a second clock cycle (Φ 2 ), with Φ 1 not equal to Φ 2 ; and
circuitry in communication with at least one stage of the storage element for individually addressing the scan cell during the test mode, the circuitry comprising an input line used to input data to the storage element in the scan cell and used to address the scan cell.
18. The scan cell of claim 17 , wherein the storage element comprises a flip flop with a master stage and a slave stage;
wherein the first stage comprises the master stage; and
wherein the second stage comprises the slave stage.
19. The scan cell of claim 18 , wherein Φ 2 =Φ 1 +HOLD, and
wherein HOLD comprises a time period to test the performance of the integrated circuit.