Semiconductor device featuring large reinforcing elements in pad area

1. A semiconductor device, comprising:

a wire-bonding electrode pad;

a plurality of interconnection formation insulating interlayers provided beneath said wire-bonding electrode pad;

a plurality of wire-bonding electrode pad interconnections provided within said plurality of interconnection formation insulating interlayers;

a first reinforcing element provided beneath said wire-bonding electrode pad and among said plurality of wire-bonding electrode pad interconnections; and

a second reinforcing element provided among said plurality of wire-bonding electrode pad interconnections,

wherein said first reinforcing element has a larger size than that of the second reinforcing element.

2. The semiconductor device as set forth in claim 1 , further comprising an insulating layer in which said first reinforcing element and said second reinforcing element are formed.

3. The semiconductor device as set forth in claim 2 , wherein said interconnections are formed in said insulating interlayer.

4. The semiconductor device as set forth in claim 3 , wherein said second reinforcing element is formed in said insulating layer except for a pad area above which said wire-bonding electrode pad is provided.

5. The semiconductor device as set forth in claim 4 , wherein at least one of said interconnections is arranged beneath said wire-bonding electrode pad.

6. The semiconductor device as set forth in claim 5 , wherein said at least one of said interconnections is defined as one of a power supply interconnection and a ground interconnection.

7. The semiconductor device as set forth in claim 6 , wherein said wire-bonding electrode pad is electrically isolated from said first reinforcing element.

8. The semiconductor device as set forth in claim 7 , wherein said wire-bonding electrode pad is composed of aluminum as a main component, and wherein said interconnections, said first reinforcing element and said second reinforcing element are composed of copper as respective main components.

9. A semiconductor device, comprising:

an interconnection formation insulating interlayer;

a plurality of interconnections formed in said interconnection formation insulating interlayer;

a wire-bonding electrode pad provided above said interconnection formation insulating interlayer so that a pad area, on which said wire-bonding electrode pad is projected, is defined on said interconnection formation insulating interlayer; and

a plurality of reinforcing elements substantially evenly formed in blank areas of said interconnection insulating interlayer in which no interconnection of said plurality of interconnections to said wire-bonding electrode pad is formed,

wherein a part of said reinforcing elements included in said pad area features a larger size than that of the remaining reinforcing elements.

10. The semiconductor device as set forth in claim 9 , wherein said interconnection formation insulating interlayer is defined as an insulating interlayer exhibiting a smaller dielectric constant than that of silicon dioxide.

11. The semiconductor device as set forth in claim 9 , wherein said wire-bonding electrode pad is composed of aluminum, and wherein said interconnections and said reinforcing elements are composed of copper.

12. The semiconductor device as set forth in claim 9 , wherein at least one of said interconnections is arranged so as to extend through said pad area.

13. The semiconductor device as set forth in claim 12 , wherein said at least one of said interconnections is defined as one of a power supply interconnection and a ground interconnection.