Semiconductor integrated circuit for reducing leak current through MOS transistors

1. A semiconductor device comprising:

a power control region within which function cells are arranged;

a basic power supply line overlapping said power control region, and positioned in a power supply interconnection layer;

a virtual power supply line arranged in said power control region in a direction perpendicular to said basic power supply line, said function cells being connected to said virtual power supply line;

a ground line arranged in said power control region in said direction perpendicular to said basic power supply line;

a switch cell including:

a metal interconnection positioned in a metal interconnection layer different from said power supply interconnection layer, and

a switch element electrically connected between said metal interconnection and said virtual power supply line; and

a via contact connected between said basic power supply line and said metal interconnection,

wherein said switch element receives a power supply voltage from said basic power supply line through said metal interconnection and said via contact to feed said received power supply voltage to said function cells within said power control region,

wherein said switch cell is positioned within power control region,

wherein said switch element is positioned adjacent to said via contact within said switch cell, and

wherein said metal interconnection is positioned between said virtual power supply line and said ground line within said switch cell.

2. The semiconductor device according to claim 1 , wherein said switch element is positioned under said basic power supply line.

3. The semiconductor device according to claim 1 , further comprising:

at least one other basic power supply line positioned in said power supply interconnection layer;

at least one other switch cell each including an other metal interconnection and an other switch element connected between said other metal interconnection and said virtual power supply line, said other metal interconnection being positioned in said metal interconnection layer; and

at least one other via contact connected between said at least one basic power supply line and said other metal interconnection.

4. The semiconductor device according to claim 3 , wherein said switch element and said other switch element are turned on at different timings when said power control region is activated.

5. The semiconductor device according to claim 1 , wherein said switch element includes a MOS switch transistor having a sufficient drive capacity for feeding the maximum allowed current of said basic power supply line to said function cells.

6. The semiconductor device according to claim 1 , wherein said function cells each including a MOS transistor; and

wherein said switch element includes a switch transistor exhibiting a off-leak current smaller than that of said MOS transistor.

7. The semiconductor device according to claim 1 , wherein said switch element includes a MOS switch transistor formed within a first well, and

wherein said function cells each including a MOS transistor formed within a second well electrically separated from said second well.

8. The semiconductor device according to claim 1 ,

wherein said switch element includes a MOS switch transistor,

wherein said function cells each including a MOS transistor, and

wherein said MOS switch transistor and said MOS transistor are formed within the same well.

9. A semiconductor device comprising:

a power control region within which function cells are arranged;

a basic ground line overlapping said power control region, and positioned in a power supply interconnection layer;

a virtual ground line arranged in said power control region in a direction perpendicular to said basic power supply line, said function cells being connected to said virtual power supply line;

a power supply line arranged in said power control region in said direction perpendicular to said basic ground line;

a switch cell including;

a metal interconnection positioned in a metal interconnection layer different from said power supply interconnection layer; and

a switch element electrically connected between said metal interconnection and said virtual ground line,

a via contact connected between said basic ground line and said metal interconnection,

wherein said switch element receives a ground level voltage from said basic ground line through said metal interconnection and said via contact to feed said received ground level voltage to said function cells within said power control region,

wherein said switch cell is positioned within power control region, and

wherein said switch element is positioned adjacent to said via contact within said switch cell, and

wherein said metal interconnection is positioned between said power supply line and said virtual ground line within said switch cell.

10. The semiconductor device according to claim 9 , wherein said switch element is positioned under said basic power supply line.

11. The semiconductor device according to claim 9 , further comprising;

at least one other basic ground line positioned in said power supply interconnection layer;

at least one other switch cell each including an other metal interconnection and an other switch element connected between said other metal interconnection and said virtual ground line, said other metal interconnection being positioned in said metal interconnection layer; and

at least one other via contact connected between said at least one basic ground line and said other metal interconnection.

12. The semiconductor device according to claim 11 , wherein said switch element and said other switch element are turned on at different timings when said power control region is activated.

13. A layout method of a semiconductor device comprising;

defining a power control region;

performing placement of function cells and a switch cell within said power control region, said function cells and said switch cell each including portions of a virtual power supply line and a ground line, and said switch cell additionally including a metal interconnection and a switch element electrically connected between said portion of said virtual power supply line and said metal interconnection;

arranging a via contact; and

arranging a basic power supply line extending in a direction perpendicular to said virtual power supply line and said ground line to overlap said power control region, and positioned in a power supply interconnection layer located over said metal interconnection, so that said via contact is connected between said basic power supply line and said metal interconnection, allowing said switch element to receive a power supply voltage from said basic power supply line through said metal interconnection and said via contact to feed said received power supply voltage to said function cells within said power control region through said portion of said virtual power supply line,

wherein said switch element is positioned adjacent to said via contact within said switch cell, and

wherein said metal interconnection is positioned between said portions of said virtual power supply line and said ground line.

14. The layout method according to claim 13 , wherein said switch cell is arranged so that said switch element is positioned under said basic power supply line.

15. The layout method according to claim 13 , wherein said switch element includes a MOS switch transistor having a sufficient drive capacity for feeding the maximum allowed current of said basic power supply line to said function cells.

16. The layout method according to claim 13 , wherein said function cells each including a MOS transistor; and

wherein said switch element includes a switch transistor exhibiting a off-leak current smaller than that of said MOS transistor.

17. The layout method according to claim 13 , wherein said switch element includes a MOS switch transistor formed within a first well, and

wherein said function cells each including a MOS transistor formed within a second well electrically separated from said second well.

18. The layout method according to claim 13 ,

wherein said switch element includes a MOS switch transistor,

wherein said function cells each including a MOS transistor, and

wherein said MOS switch transistor and said MOS transistor are formed within the same well.