Detecting switching of access elements of phase change memory cells
View Patent ↗A memory includes a storage element (OUM) made of a phase-change material for storing a logic value and an access element (OTS) switching from a higher resistance condition to a lower resistance condition in response to a selection of the memory cell, the access element in the higher resistance condition decoupling the storage element from a read circuit and in the lower resistance condition coupling the storage element to the read circuit. The read circuit includes a sense amplifier to determine the logic value stored in the memory cell according to an electrical quantity associated with the memory cell. The read circuit further includes a detector that detects the switching of the access element by comparison to a delayed waveform or sensing a change in the column rate of change, and a circuit to enable the sense amplifier in response to the detection of the switching of the access element.
1. A method comprising:
providing a read biasing current and a second read current lower than the read biasing current;
applying the read biasing current to a memory cell in response to the selection of the memory cell;
detecting a first steady condition of the memory cell corresponding to the read biasing current;
sensing a first measuring voltage in response to the detection of the first steady condition;
applying the second read current to the memory cell in response to the sensing of the first measuring voltage;
detecting a second steady condition of the memory cell corresponding to the second read current;
sensing a second measuring voltage in response to the detection of the second steady condition; and
determining a logic value stored in the memory cell according to the first and the second measuring voltages.
2. The method according to claim 1 , wherein detecting the second steady condition includes identifying a first change of rate of an electrical quantity, and detecting the first steady condition includes identifying a second change of rate after the first change of rate.
3. The method according to claim 2 , wherein detecting the first and second changes of rate includes delaying the electrical quantity by a predetermined period and identifying the corresponding change of rate when the delayed electrical quantity reaches the electrical quantity within a predetermined offset, the offsets for the first and second changes of rate having opposite signs.
4. A phase change memory comprising:
a circuit coupled to a memory cell to provide a read biasing current and a second read current lower than the read biasing current, said circuit to apply the read biasing current to the memory cell in response to a selection of the memory cell;
a first detector coupled to the memory cell to detect a first steady condition of the memory cell corresponding to the read biasing current;
a first device coupled to the memory cell to sense a first measuring voltage in response to the detection of the first steady condition and to apply the second read current to the memory cell in response to the sensing of the first measuring voltage;
a second detector coupled to the memory cell to detect a second steady condition of the memory cell corresponding to the second read current;
a second device coupled to the memory cell to sense a second measuring voltage in response to the detection of the second steady condition; and
a third device coupled to the memory cell to determine a logic value stored in the memory cell according to the first and second measuring voltages.
5. The memory of claim 4 wherein the second detector to detect the second steady condition to identify a first change of rate of an electrical quantity, and said first detector to detect the first steady condition to identify a second change of rate after the first change of rate.
6. The memory of claim 5 wherein said second detector to detect the second steady condition and said first detector to detect said first steady condition to detect the first and second changes of rate by delaying the electrical quantity by a predetermined period and identifying the corresponding change of rate when the delayed electrical quantity reaches the electrical quantity within a predetermined offset, the offset for the first and second changes of rate having opposite signs.
7. The memory of claim 4 wherein said memory is a phase-change memory including a chalcogenide.
8. The memory of claim 7 wherein said phase-change memory includes a storage element and an access element.
9. The memory of claim 8 wherein said access element includes a threshold switch element made of a single phase of material.
10. A system comprising:
a controller; and
a phase-change memory coupled to said controller to provide a read biasing current and a second read current lower than the read biasing current, to apply the read biasing current to a memory cell in response to the selection of the memory cell, to detect a first steady condition of the memory cell corresponding to the read biasing current, to sense a first measuring voltage in response to the detection of the first steady condition, to apply the second read current to the memory cell in response to the sensing of the first measuring voltage, to detect a second steady condition of the memory cell corresponding to the second read current, to sense a second measuring voltage in response to the detection of the second steady condition, and to determine a logic value stored in the memory cell according to the first and second measuring voltages.
11. The system of claim 10 wherein said memory to identify a first change of rate of an electrical quantity and identifies a second change of rate after the first change of rate.
12. The system of claim 11 , said memory to delay the electrical quantity by a predetermined period and identify the corresponding change of rate when the delayed electrical quantity reaches the electrical quantity within a predetermined offset, the offsets for the first and second changes of rate having opposite signs.