CMOS image sensor and method for manufacturing the same
View Patent ↗A CIS and a method of manufacturing the same are provided. The CIS includes a device isolation layer formed on a device isolation region of a substrate of a first conductive type, the substrate including an active region and the device isolation region, the active region including a photodiode region and a transistor region; a high-concentration diffusion region of the first conductive type formed around the device isolation layer; a gate electrode formed on the active region of the substrate with a gate insulation layer interposed therebetween; a low-concentration diffusion region of a second conductive type formed on the photodiode region and spaced a predetermined distance apart from the device isolation layer; and a high-concentration diffusion region of a second conductive type formed on the transistor region.
1. A method for manufacturing a CIS (complementary metal oxide silicon image sensor), the method comprising:
forming a device isolation layer on a device isolation region of a substrate of a first conductive type;
forming a high-concentration first conductive type diffusion region around the device isolation layer;
forming a gate electrode on an active region of the substrate with a gate insulation layer interposed therebetween;
forming a low-concentration second conductive type diffusion region on a photodiode region of the active region spaced a predetermined distance apart from the device isolation layer; and
forming a high-concentration second conductive type diffusion region on a transistor region of the active region,
wherein the forming of the device isolation layer and the forming of the high-concentration first conductive type diffusion region comprises:
implanting oxygen ions into the device isolation region;
implanting high-concentration first conductive impurity ions into the device isolation region after implanting the oxygen ions; and
performing an annealing process to the substrate into which the oxygen ions and the high concentration first conductive impurity ions have been implanted.
2. The method according to claim 1 , wherein the high-concentration first conductive type diffusion region isolates the device isolation layer from the low-concentration second conductive type diffusion region.
3. The method according to claim 1 , wherein the high-concentration first conductive type diffusion region surrounds the device isolation layer except for a top surface of the device isolation layer.
4. The method according to claim 1 , wherein the forming of the device isolation layer and the high-concentration first conductive type diffusion region comprises:
forming a pad oxide layer on the substrate;
coating a photosensitive film on the pad oxide layer and patterning the pad oxide to expose the device isolation region;
implanting the oxygen ions and then the high-concentration first conductive impurity ions into the device isolation region using the patterned photosensitive film as a mask; and
performing the annealing process to the substrate into which the oxygen ions and the high-concentration first conductive impurity ions have been implanted.
5. The method according to claim 1 , wherein the high-concentration first conductive type diffusion region is formed deeper into the substrate than the device isolation layer.
6. The method according to claim 1 , wherein the high-concentration first conductive type diffusion region is formed with a junction depth of 1 to 2 μm.
7. The method according to claim 1 , wherein the high-concentration first conductive type diffusion region is formed by implanting B + ions into the device isolation region of the substrate.
8. The method according to claim 1 , further comprising forming a low-concentration second conductive type diffusion region on the transistor region of the substrate.