LDMOS device and method for manufacturing the same
View Patent ↗Provided is a LDMOS device and method for manufacturing. The LDMOS device includes a second conductive type buried layer formed in a first conductive type substrate. A first conductive type first well is formed in the buried layer and a field insulator with a gate insulating layer at both sides are formed on the first well. On one side of the field insulator is formed a first conductive type second well and a source region formed therein. On the other side of the field insulator is formed an isolated drain region. A gate electrode is formed on the gate insulating layer on the source region and a first field plate is formed on a portion of the field insulator and connected with the gate electrode. A second field plate is formed on another portion of the field insulator and spaced apart from the first field plate.
1. A method for manufacturing a lateral diffused MOS device, the method comprising:
forming a buried layer doped with a second conductive type impurity in a first conductive type substrate;
forming a first well doped with the first conductive type impurity in the buried layer;
forming a field insulator on a surface of the first well;
forming a gate insulating layer on a surface of the first well at both sides of the field insulator;
forming a second well doped with the first conductive type impurity in the first well at one side of the field insulator;
forming a source region in a surface of the second well;
forming a drain region isolated from the source region in the surface of the first well at the other side of the field insulator;
forming a gate electrode on the gate insulating layer on the source region;
forming a first field plate connected with the gate electrode on a predetermined portion of the field insulator; and
forming a second field plate spaced apart by a predetermined spacing from the first field plate on another predetermined portion of the field insulator.
2. The method according to claim 1 , wherein the gate electrode, the first field plate and the second field plate are formed at the same time.
3. The method according to claim 1 , wherein the gate electrode, the first field plate and the second field plate are formed using a same mask.
4. The method according to claim 1 , wherein the gate electrode, the first field plate and the second field plate are formed of a same polysilicon material.
5. The method according to claim 1 , wherein forming the gate electrode, the first field plate, and the second field plate comprises:
forming a polysilicon layer on an entire surface of the substrate including the gate insulating layer and the field insulator;
forming a photoresist pattern exposing the polysilicon layer on a predetermined portion of the source region, the drain region and the field insulator; and
etching the polysilicon layer using the photoresist pattern as a mask.
6. The method according to claim 1 , further comprising forming sidewall spacers on the gate electrode, the first field plate, and the second field plate.
7. The method according to claim 1 , wherein the first conductive type is P-type and the second conductive type is N-type.
8. The method according to claim 1 , further comprising forming a first doping region doped with the first conductive type impurity in the surface of the second well.
9. The method according to claim 1 , wherein the source region is doped with the second conductive type impurity.
10. The method according to claim 1 , wherein the second field plate is formed such that a bias applied to the second field plate is different from a bias applied to the first field plate.