Booster circuit
View Patent ↗A booster circuit for boosting and outputting a voltage between a power supply potential line and a reference potential line using a capacitor connected between a boosted voltage output node and the reference potential line that includes a first switch for separating the capacitor from the boosted voltage output node while a boosting operation is suspended, a second switch connected in parallel to the capacitor and being conductive while the boosting operation is suspended, and an electric path between the power supply potential line and the boosted voltage output node while the boosting operation is suspended.
1. A booster circuit for boosting a voltage between a power supply potential and a ground potential using a capacitor connected between a boosted voltage output node and the ground potential, the booster circuit comprising:
a first switch for separating the capacitor from the boosted voltage output node while a boosting operation is suspended;
a second switch connected to the ground potential in parallel to the capacitor and being conductive while the boosting operation is suspended; and
an electric path between the power supply potential and the boosted voltage output node while the boosting operation is suspended.
2. The booster circuit according to claim 1 , wherein the electric path comprises a transistor.
3. The booster circuit according to claim 1 , wherein the electric path comprises a resistance.
4. The booster circuit according to claim 1 , further comprising a first boosted voltage application circuit formed by a semiconductor integrated circuit and activated by a potential of the boosted voltage output node while the boosting operation is suspended.
5. The booster circuit according to claim 4 , wherein the boosting operation is performed by a charge pump circuit.
6. The booster circuit according to claim 5 , further comprising a circuit as the first boosted voltage application circuit for outputting a signal to fix the charge pump circuit to a predetermined state while the boosting operation is suspended.
7. The booster circuit according to claim 4 , further comprising a second boosted voltage application circuit connected to the capacitor.
8. The booster circuit according to claim 1 , further comprising:
a first circuit for generating a signal necessary to activate the boosting operation, the first circuit being connected to the boosted voltage output node while the boosting operation is suspended; and
a second circuit for receiving a boosted voltage generated in the capacitor, the second circuit being electrically separated from the boosted voltage output node while the boosting operation is suspended.
9. The booster circuit according to claim 8 , wherein the first circuit generates a boosting clock signal.
10. A booster circuit comprising:
a first switch connected between first and second boosted voltage output nodes and separating the first boosted voltage output node from the second boosted voltage output node while a boosting operation is suspended;
a second switch connected between the second boosted voltage output node and a reference potential and being conductive while the boosting operation is suspended so that a potential of the second boosted voltage output node is the reference potential; and
an electric path between a power supply potential and the first boosted voltage output node to maintain a power supply potential at the first boosted voltage output node while the boosting operation is suspended.