Global address space management

1. A method to access data in a System-On-a-Chip (SOC) unit, comprising:

receiving a memory address that is part of a contiguous address space that includes addresses corresponding to an on-chip memory and an off-chip memory;

determining whether said memory address corresponds to an on-chip memory location or an off-chip memory location;

decoding said memory address and accessing an on-chip memory via a first controller if said memory address corresponds to an on-chip memory location; and

decoding said memory address and accessing an off-chip memory via a second controller if said memory address corresponds to an off-chip memory location.

2. The method of claim 1 , wherein the first controller is a node controller, the on-chip memory is Static Random Access Memory (SRAM), the second controller is a memory controller and the off-chip memory is Random Access Memory (RAM).

3. The method of claim 1 , wherein said memory address is received from a plurality of threads that utilize a combined address space including on-chip memory addresses and off-chip memory addresses.

4. The method of claim 1 , wherein said memory address is received from one of a plurality of processors configured to utilize a combined address space that includes on-chip memory addresses and off-chip memory addresses.

5. The method of claim 1 , wherein in response to receiving an address, said first controller determines whether said address corresponds to on-chip memory or off-chip memory and decodes the received address if the received address corresponds to an on-chip memory location.

6. A System-On-a-Chip (SOC), comprising:

on-chip memory having a first set of addresses that are part of a contiguous address space that further includes a second set of addresses that correspond to an off-chip memory;

a first controller; and

a second controller;

wherein said first controller is enabled to decode addresses mapped to said on-chip memory and said second controller is enabled to decode addresses mapped to said off-chip memory.

7. The System on Chip (SOC) of claim 6 , wherein the first controller is a node controller, the on-chip memory is Static Random Access Memory (SRAM), the second controller is a memory controller and the off-chip memory is Random Access Memory (RAM).

8. The System on Chip (SOC) of claim 6 , further comprising a plurality of processors configured to utilize a combined address space that includes on-chip memory addresses and off-chip memory addresses.

9. The System on Chip (SOC) of claim 6 , wherein a plurality of threads utilize a combined address space that includes on-chip memory addresses and off-chip memory addresses.

10. The System on Chip (SOC) of claim 6 , wherein in response to receiving an address, said first controller determines whether said address corresponds to on-chip memory or off-chip memory and decodes the received address if the received address corresponds to an on-chip memory location.

11. A Chip System-On-a-Chip (SOC) comprising:

a plurality of processors;

on-chip memory having a first set of addresses that are part of a contiguous address space that further includes a second set of addresses that correspond to an off-chip memory;

a first means to decode addresses mapped to on-chip memory;

a second means to decode addresses mapped to off-chip memory;

wherein said first means and said second means receive a memory address from one of the plurality of processors.

12. The SOC of claim 11 , wherein the first means is a node controller, the on-chip memory is Static Random Access Memory (SRAM), the second means is a memory controller and the off-chip memory is Random Access Memory (RAM).

13. The SOC of claim 11 , wherein the first means is configured to determine whether an address corresponds to on-chip memory or off-chip memory.

14. The SOC of claim 11 , wherein the first means and second means are configured to receive addresses from a plurality of threads.