Semiconductor device and manufacturing method thereof
View Patent ↗In a semiconductor device having SiC vertical trench MOSFETs, it is aimed to prevent the generation of large scattering in the channel resistance without largely increasing the average value of channel resistance. A 4H-SiC substrate having a major face thereof that is generally a {0001} face and having an off angle α. The trench is formed with the standard deviation σ in scattering of the angle formed by a trench side wall face and a substrate major face within a wafer face. By setting the designed value of the angle formed by the trench side wall face and the substrate major face at an any angle ranging from [(60 degrees)+2σ] to [(90 degrees)−tan −1 (0.87×tan α)−2σ] in forming the trench in the SiC substrate, a semiconductor device in which the angle formed by the trench side wall face and the substrate major face is 60 degrees or more but not more than [(90 degrees)−tan −1 (0.87×tan α)] can be obtained.
1. A semiconductor device comprising:
at least one SiC semiconductor layer having an azimuth of a major face thereof that is generally a {0001} face and having an off angle α in a range of 4-8°; and
at least one trench in the semiconductor layer having side walls, with normal lines of faces of the side walls extending generally in a <1-100> direction when projected on the major face of the semiconductor layer,
wherein an angle formed by the side wall faces of the trench and the major face of the semiconductor layer is 60 degrees or more but not more than [(90 degrees)−tan −1 (0.87×tan α)].
2. The semiconductor device according to claim 1 , wherein a plurality of unit structures each including the trench is formed at a predetermined pitch, which is not more than two times a pitch of the unit structure where the side wall faces of the trench would form an angle of 90 degrees against the major face of the SiC semiconductor layer.
3. The semiconductor device according to claim 2 , wherein the azimuths of the trench side wall faces are off from any of the {1-100} face family of SiC into the <0001> direction.
4. The semiconductor device according to claim 3 , wherein an off direction of the major face of the SiC semiconductor layer is generally in a <11-20> direction.
5. The semiconductor device according to claim 2 , wherein an off direction of the major face of the SiC semiconductor layer is generally in a <11-20> direction.
6. The semiconductor device according to claim 1 , wherein the azimuths of the trench side wall faces are off from any of the {1-100} face family of SiC into the <0001> direction.
7. The semiconductor device according to claim 6 , wherein an off direction of the major face of the SiC semiconductor layer is generally in a <11-20> direction.
8. The semiconductor device according to claim 1 , wherein an off direction of the major face of the SiC semiconductor layer is generally in a <11-20> direction.
9. The semiconductor device according to claim 1 , wherein the side wall faces of the trench are not parallel to an off direction of the major face of the SiC semiconductor layer.
10. A method of manufacturing a semiconductor device comprising the steps of:
providing at least one SiC semiconductor layer having an azimuth of a major face thereof that is generally a {0001} face and having an off angle α in a range of 4-8°; and
forming at least one trench in the semiconductor having side walls, with normal lines of faces of the side walls extending generally in a <1-100> direction when projected on the major face of the semiconductor layer, with an angle formed by the side wall faces of the trench and the major face of the semiconductor layer being 60 degrees or more but not more than [(90 degrees)−tan −1 (0.87×tan α)].
11. The method according to claim 10 , wherein the trench forming step includes setting a design value of the angle formed by the trench side wall faces and the major face of the semiconductor layer at any angle within the range from (60 degrees+2σ) to [(90 degrees)−tan −1 (0.87×tan α)−2σ], where σ represents a standard deviation of scattering in the angle formed by the trench side wall faces and the major face of an SiC semiconductor layer within a wafer face of a wafer forming the semiconductor layer.
12. The method according to claim 11 , further including the steps of:
accumulating polysilicon on the trench side wall faces; and
thermally oxidizing the polysilicon to form a gate oxide film.
13. The method according to claim 10 , wherein a plurality of unit structure including the trench is formed at a predetermined pitch, which is not more than two times a pitch of the unit structure where the side wall faces of the trench would form an angle of 90 degrees against the major face of the SiC semiconductor layer.
14. The method according to claim 13 , wherein the azimuths of the trench side wall faces are off from any of the {1-100} face family of SiC into the <0001> direction.
15. The method according to claim 14 , wherein an off direction of the major face of the SiC semiconductor layer is generally in a <11-20> direction.
16. The method according to claim 13 , wherein an off direction of the major face of the SiC semiconductor layer is generally in a <11-20> direction.
17. The method according to claim 10 , wherein the azimuths of the trench side wall faces are off from any of the {1-100} face family of SiC into the <0001> direction.
18. The method according to claim 17 , wherein an off direction of the major face of the SiC semiconductor layer is generally in a <11-20> direction.
19. The method according to claim 10 , wherein an off direction of the major face of the SiC semiconductor layer is generally in a <11-20> direction.
20. The method according to claim 10 , wherein the side wall faces of the trench are not parallel to an off direction of the major face of the SiC semiconductor layer.