Fabricating method for a metal oxide semiconductor transistor

1. A method of fabricating a metal oxide semiconductor (MOS) transistor, comprising:

providing a substrate;

forming a gate structure on the substrate;

forming an offset spacer on respective sidewalls of the gate structure;

performing a first ion implantation process to form a lightly doped drain (LDD) in the substrate beside the gate structure;

forming a spacer on respective sidewalls of the offset spacer;

performing a second ion implantation process to form a source and a drain in the substrate beside the spacer;

forming a metal silicide layer on the surface of the source and the drain;

forming an oxide layer only on the surface of the metal silicide layer, wherein the oxide layer fully covers the surface of the metal silicide layer;

removing the spacer after the oxide layer is formed; and

forming an etching stop layer over the substrate to cover the oxide layer, the offset spacer and the gate structure.

2. The method of claim 1 , wherein the step of forming the oxide layer on the surface of the metal silicide layer includes performing an oxygen (O 2 ) plasma treatment.

3. The method of claim 1 , wherein the material constituting the spacers comprises silicon nitride.

4. The method of claim 1 , wherein the oxide layer has a thickness between about 10 Å to 30 Å.

5. The method of claim 1 , wherein the material constituting the etching stop layer comprises silicon nitride.

6. The method of claim 1 , wherein the material constituting the metal silicide is selected from a group consisting of nickel silicide, cobalt silicide, platinum silicide, palladium silicide, molybdenum silicide and an alloy of some of the above metal silicide.

7. The method of claim 1 , wherein the material constituting the offset spacers comprises silicon oxide.

8. The method of claim 1 , wherein the offset spacer includes an oxide/nitride/oxide (ONO) composite stack layer.

9. A method of fabricating a metal oxide semiconductor (MOS) transistor, comprising:

providing a substrate;

forming a gate structure on the substrate;

forming an offset spacer on respective sidewalls of the gate structure;

performing a first ion implantation process to form a lightly doped drain (LDD) in the substrate beside the gate structure;

forming a spacer on respective sidewalls of the offset spacer;

performing a second ion implantation process to form a source and a drain in the substrate beside the spacer;

forming a metal silicide layer on the surface of the source and the drain;

removing a portion of the spacer using hot phosphoric acid so that a portion of the spacer remains;

rinsing with de-ionized water (DI water) to form an oxide layer on the surface of the metal silicide layer; and

removing the remaining spacer using hot phosphoric acid; and

forming an etching stop layer over the substrate to cover the oxide layer, the offset spacer and the gate structure.

10. The method of claim 9 , wherein the material constituting the spacers comprises silicon nitride.

11. The method of claim 9 , wherein the oxide layer has a thickness between about 10 Å to 30 Å.

12. The method of claim 9 , wherein the material constituting the etching stop layer comprises silicon nitride.

13. The method of claim 9 , wherein the material constituting the metal silicide is selected from a group consisting of nickel silicide, cobalt silicide, platinum silicide, palladium silicide, molybdenum silicide and an alloy of some of the above metal silicide.

14. The method of claim 9 , wherein the material constituting the offset spacers comprises silicon oxide.

15. The method of claim 9 , wherein the offset spacer includes an oxide/nitride/oxide (ONO) composite stack layer.

16. A method of fabricating a metal oxide semiconductor (MOS) transistor, comprising:

providing a substrate;

forming a gate structure on the substrate;

forming an offset spacer on respective sidewalls of the gate structure;

performing a first ion implantation process to form a lightly doped drain (LDD) in the substrate beside the gate structure;

forming a spacer on respective sidewalls of the offset spacer;

performing a second ion implantation process to form a source and a drain in the substrate beside the spacer;

forming a metal silicide layer on the surface of the source and the drain;

removing a portion of the spacers using hot phosphoric acid so that a portion of the spacer remains;

performing a deionized water and ozone (DI-O 3 ) treatment to form an oxide layer on the surface of the metal silicide layer; and

removing the remaining spacer using hot phosphoric acid; and

forming an etching stop layer over the substrate to cover the oxide layer, the offset spacer and the gate structure.

17. The method of claim 16 , wherein the material constituting the spacers comprises silicon nitride.

18. The method of claim 16 , wherein the oxide layer has a thickness between about 10 Å to 30 Å.

19. The method of claim 16 , wherein the material constituting the etching stop layer comprises silicon nitride.

20. The method of claim 16 , wherein the material constituting the metal silicide is selected from a group consisting of nickel silicide, cobalt silicide, platinum silicide, palladium silicide, molybdenum silicide and an alloy of some of the above metal silicide.

21. The method of claim 16 , wherein the material constituting the offset spacers comprises silicon oxide.

22. The method of claim 16 , wherein the offset spacer includes an oxide/nitride/oxide (ONO) composite stack layer.