IP Library Granted Patent US 9,001,899
Granted Patent B2
US 9,001,899 · App. 11/532,417 · Granted Apr 7, 2015

Video information processing system with selective chroma deblock filtering

Inventor: Zhongli He (Austin, TX)
Assignee: Freescale Semiconductor, Inc.
H04N19/00139H04N19/00315H04N19/00066H04N19/00884H04N19/00278H04N19/00909H04N19/00896H04N19/00206
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Quick Facts
Patent No.
US 9,001,899
App. No.
11/532,417
Granted
Apr 7, 2015
Kind
B2
Abstract

A video information processing system including a processing circuit and a deblocking filter. The processing circuit provides video information including a chroma component and a luma component. The deblocking filter has an input receiving the video information and an output providing filtered video information, and is configured to selectively disable chroma deblock filtering while luma deblock filtering is enabled. The processing circuit may include a video encoder or a video decoder. The processing circuit may further include control logic providing a control signal to disable chroma deblock filtering within either or both the encoder and decoder. The video encoder may incorporate control information in the output bitstream to control deblock filtering in the downstream decoder to maintain consistency between the encoder and the decoder.

Claims (43)

1. A deblocking filter for deblock filtering video information which includes luma information and chroma information, said deblocking filter comprising:

a luma deblocking filter which deblock filters said luma information;

a chroma deblocking filter which deblock filters said chroma information; and

control logic which is configured to disable said chroma deblocking filter to bypass the functions performed for chroma deblock filtering including bypassing data loading of chroma information for chroma deblock filtering, wherein said chroma deblocking filter is disabled for an entire slice of said video information while said luma deblocking filter is enabled for said entire slice of said video information.

2. The deblocking filter of claim 1 , further comprising:

a memory for storing said luma information and said chroma information; and

wherein said control logic comprises at least one switching device which selectively decouples said chroma deblocking filter from said memory.

3. The deblocking filter of claim 1 , further comprising:

a boundary strength circuit having an input for receiving said luma information and an output for providing a boundary strength signal;

said chroma deblocking filter having a strength select input receiving said strength signal; and

wherein said control logic comprises a switch device for selectively decoupling said output of said boundary strength circuit from said strength select input of said chroma deblocking filter.

4. The deblocking filter of claim 1 , wherein said chroma deblocking filter comprises a blue luma difference deblocking filter and a red luma difference deblocking filter, and wherein said control logic is configured to selectively enable and disable said blue and red luma difference deblocking filters.

5. The deblocking filter of claim 1 , further comprising:

a memory for storing said video information; and

a processor, coupled to said memory, wherein said processor is configured to implement said luma deblocking filter, said chroma deblocking filter and said control logic and to selectively disable chroma deblock filtering for said entire slice of said video information.

6. The deblocking filter of claim 5 , wherein said processor controls storing of said video information into said memory, and wherein said processor selectively bypasses storage of said chroma information in said memory when chroma deblock filtering is disabled.

7. A video information processing system, comprising:

a processing circuit for providing video information including a chroma component and a luma component; and

a deblocking filter having an input receiving said video information and an output providing filtered video information, wherein said deblocking filter is configured to disable chroma deblock filtering to bypass the functions performed for chroma deblock filtering including bypassing data loading of chroma information for chroma deblock filtering, wherein said chroma debock filtering is disabled for an entire slice of said video information while luma deblock filtering is enabled for said entire slice of said video information.

8. The video information processing system of claim 7 , wherein said processing circuit comprises:

a video encoder which provides said video information as reconstructed video information; and

control logic which provides a filter control signal to said deblocking filter to disable chroma deblock filtering and enable luma deblock filtering for said entire slice of said video information while processing said reconstructed video information.

9. The video information processing system of claim 8 , wherein said video encoder generates residual information, converts said residual information into said reconstructed video information, encodes said residual information into encoded information within an encoded bitstream, and incorporates control information in said encoded bitstream associated with said encoded information, and wherein said control information indicates disabling chroma deblock filtering and enabling luma deblock filtering.

10. The video information processing system of claim 7 , wherein said processing circuit comprises:

a video decoder which provides said video information as decoded reconstructed video information; and

control logic which provides a filter control signal to said deblocking filter to disable chroma deblock filtering and enable luma deblock filtering for said entire slice of said video information while processing said decoded reconstructed video information.

11. The video information processing system of claim 10 , wherein said video decoder is configured to decode an input encoded bitstream into said decoded reconstructed video information and to retrieve control information in said encoded bitstream associated with said decoded reconstructed video information, and wherein said control information indicates disabling chroma deblock filtering and enabling luma deblock filtering.

12. The video information processing system of claim 7 , wherein said processing circuit comprises a memory which stores said video information, and wherein said deblocking filter comprises a post processor for filtering said video information.

13. The video information processing system of claim 7 , wherein said deblocking filter comprises:

a memory for storing said video information; and

a processor, coupled to said memory, wherein said processor is configured to perform luma deblock filtering and chroma deblock filtering;

wherein said processor selectively disables chroma deblock filtering for said entire slice of said video information.

14. The video information processing system of claim 7 , wherein said processing circuit comprises a video encoder which encodes said video information into at least one slice comprising deblocking filter control information indicating disabling chroma deblock filtering while enabling luma deblock filtering.

15. The video information processing system of claim 7 , wherein said processing circuit comprises a video decoder which decodes at least one slice of encoded information while chroma deblock filtering is disabled and while luma deblock filtering is enabled.

16. A method of deblock filtering a slice of video information by a video processing system, comprising:

receiving a slice of unfiltered luma information and unfiltered chroma information;

disabling a chroma deblock filter for the entire slice, including bypassing the functions performed for chroma deblock filtering including bypassing data loading of chroma information for chroma deblock filtering;

deblock filtering the unfiltered luma information by a luma deblock filter to provide filtered luma information; and

combining the filtered luma information with the unfiltered chroma information into a slice of output filtered video information.

17. The method of claim 16 , wherein said disabling chroma deblock filtering comprises decoupling at least one chroma deblocking filter.

18. The method of claim 17 , wherein said decoupling a chroma deblocking filter comprises decoupling an input and an output of the at least one chroma deblocking filter.

19. The method of claim 16 , further comprising encoding the slice of output filtered video information to include deblocking filter control information which indicates chroma deblock filtering is disabled and luma deblock filtering is enabled for the slice.

20. The method of claim 16 , further comprising decoding the slice of output filtered video information while chroma deblock filtering is disabled and while luma deblock filtering is enabled.

Assignments (29)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
PATENT RELEASE Recorded Aug 17, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 039707/0471 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 23, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 036864/0886 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Mar 15, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 024085/0001 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 15, 2006
From: HE, ZHONGLI
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 018263/0097 →
Continuity (1)
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