Contrast interposer stacking system and method
View Patent ↗The present description provides increased contrast between interposer and leads in a stack embodiment that employs an interposer that extends beyond a boundary or perimeter established by the leads of the constituent IC devices.
1. A circuit module comprised of:
first and second leaded packaged integrated circuits in stacked disposition with the first leaded package being disposed above the second leaded package, each of which first and second leaded packaged integrated circuits having a body emergent from which are leads that each have a shoulder and foot, the shoulders each having a head;
a first interposer for electrical connection between the first and second leaded packaged integrated circuits, the first interposer having a dark portion and a light portion defined on a lower planar surface of the interposer and delineable with an imaginary line K, with the light portion being more reflective of light than is the dark portion and the first interposer having an external section and an internal section disposed on different sides of a line L defined by termini of a plurality of the feet of the leads of the first leaded packaged integrated circuit, the external section of the first interposer being further from the first packaged integrated circuit than is the internal section, and imaginary line K being closer to the body of the second packaged integrated circuit than is line L, wherein the dark portion extends through the line L.
2. The circuit module of claim 1 in which the dark portion of the first interposer is realized with a contrast layer.
3. The circuit module of claim 1 in which the dark portion of the first interposer is realized with colored PCB material.
4. The circuit module of claim 1 in which the dark portion of the first interposer is realized with dyed PCB material.
5. The circuit module of claim 1 in which the first and second leaded packaged integrated circuits are flash memory devices.
6. The circuit module of claim 1 further comprising:
a second interposer for electrical connection between the first and second leaded packaged integrated circuits, the second interposer having a dark portion and a light portion delineable with an imaginary line K with the light portion being more reflective of light than is the dark portion and the second interposer having an external section and an internal section disposed on different sides of a line L defined by termini of a plurality of the feet of the leads of the first leaded packaged integrated circuit, the external section of the second interposer being further from the first packaged integrated circuit than is the internal section, and imaginary line K being closer to the body of the second packaged integrated circuit than is line L.
7. The circuit module of claim 1 in which a first trace extends onto the external section of the first interposer.
8. The circuit module of claim 1 in which the first trace connects two non-adjacent ones of upper or lower connective elements of the first interposer.
9. The circuit module of claim 6 in which thermally conductive adhesive is disposed between the first and second leaded packaged integrated circuits.
10. The circuit module of claim 1 in which a secondary first trace extends onto the external section of the first interposer.
11. The circuit module of claim 1 in which vias are disposed perpendicularly to first and second substantially planar surfaces of the first interposer.
12. The circuit module of claim 1 in which there are no buried layers in the first interposer.
13. The circuit module of claim 6 in which the first and second interposers are comprised of printed circuit board.
14. The circuit module of claim 6 in which the first and second interposers distance the first leaded packaged integrated circuit from the second leaded packaged integrated circuit and between the first and second interposers there resides a thermally conductive material.
15. The circuit module of claim 6 in which the first and second leaded packaged integrated circuits are memory circuits.
16. The circuit module of claim 6 in which the first and second packaged integrated circuits are flash memory circuits.
17. The circuit module of claim 1 in which the first and second leaded packaged integrated circuits are TSOP packaged memory circuits.
18. The circuit module of claim 1 in which thermally conductive material resides in a space between the first and second leaded packaged integrated circuits.
19. The circuit module of claim 1 in which the space between the first and second leaded integrated circuits is an air gap.
20. The circuit module of claim 6 in which the first and second interposers are etched printed circuit board patterned to connect a no-connect one of the leads of the second leaded packaged integrated circuit with an active lead of the first leaded packaged integrated circuit.