Granted Patent B2

US 7,579,243 · App. 11/535,345 · Granted Aug 25, 2009

Abstract

Claims (62)

1. A method for forming split gate memory cells using a semiconductor substrate, comprising:

forming a sacrificial layer;

patterning the sacrificial layer to form a sacrificial structure with a first sidewall and a second sidewall;

forming a layer of nanocrystals over the semiconductor substrate;

depositing a first polysilicon layer over the semiconductor substrate;

performing an anisotropic etch on the first polysilicon layer to form a first polysilicon sidewall spacer adjacent the first sidewall and a second polysilicon sidewall spacer adjacent the second sidewall;

removing the sacrificial structure to leave the first polysilicon sidewall spacer and the second sidewall spacer;

depositing a second polysilicon layer over the first and second polysilicon sidewall spacers and the semiconductor substrate; and

performing an anisotropic etch on the second polysilicon layer to form a third polysilicon sidewall spacer adjacent to a first side of the first polysilicon sidewall spacer and a fourth polysilicon sidewall spacer adjacent to a first side of the second polysilicon sidewall spacer.

2. The method of claim 1 , wherein:

the step of forming the layer of nanocrystals occurs before the step performing an anisotropic etch on the first polysilicon layer; and

the step performing an anisotropic etch on the first polysilicon layer results in the first polysilicon sidewall spacer being over a first portion of the layer of nanocrystals and the second polysilicon sidewall spacer being over a second portion of the layer of nanocrystals.

3. The method of claim 2 , wherein:

the step of performing an anisotropic etch on the first polysilicon layer is further characterized by the first polysilicon sidewall spacer being a control gate of a first split gate memory cell and the second polysilicon sidewall spacer being a control gate of a second split gate memory cell; and

the step of performing an anisotropic etch on the second polysilicon layer is further characterized by the third polysilicon sidewall spacer being a select gate of the first split gate memory cell and the second polysilicon sidewall spacer being a select gate of the second split gate memory cell.

4. A method of claim 1 , wherein:

the step of forming the layer of nanocrystals occurs after the step performing an anisotropic etch on the first polysilicon layer and before the step of performing an anisotropic etch on the second polysilicon layer; and

the step performing an anisotropic etch on the second polysilicon layer results in the third polysilicon sidewall spacer being over a first portion of the layer of nanocrystals and the fourth polysilicon sidewall spacer being over a second portion of the layer of nanocrystals.

5. The method of claim 2 , wherein:

the step of performing an anisotropic etch on the first polysilicon layer is further characterized by the first polysilicon sidewall spacer being a select gate of a first split gate memory cell and the second polysilicon sidewall spacer being a select gate of a second split gate memory cell; and

the step of performing an anisotropic etch on the second polysilicon layer is further characterized by the third polysilicon sidewall spacer being a control gate of the first split gate memory cell and the second polysilicon sidewall spacer being a control gate of the second split gate memory cell.

6. The method of claim 1 , further comprising removing, prior to the step of performing an anisotropic etch on the second polysilicon layer, a first portion of the second polysilicon layer, the first portion being adjacent to a second side of the third polysilicon sidewall spacer.

7. The method of claim 1 , wherein:

the step of performing an anisotropic etch of the first polysilicon layer is further characterized by the first and second polysilicon sidewall spacers having a first height; and

the step of performing an anisotropic etch of the second polysilicon layer is further characterized by the third and fourth polysilicon sidewall spacers having a second height lower than the first height.

8. The method of claim 7 , further comprising siliciding top portions of the first, second, third, and fourth polysilicon sidewall spacers.

9. The method of claim 1 , further comprising performing a threshold adjust implant after removing the sacrificial structure and before depositing the second polysilicon layer.

10. The method of claim 9 , further comprising forming a gate dielectric on the substrate between the first and second polysilicon sidewall spacers after performing the threshold adjust implant.

11. The method of claim 10 , wherein:

the step of forming a layer of nanocrystals results in nanocrystals on the first sides of the first and second polysilicon sidewalls; and

the step of forming the gate dielectric has the effect of removing the nanocrystals on the first sides of the first and second polysilicon sidewalls.

12. The method of claim 1 , further comprising performing a source/drain implant after forming the third and fourth polysilicon sidewall spacers using the first, second, third, and fourth polysilicon sidewall spacers as masks.

13. The method of claim 11 , further comprising forming, prior to performing the source/drain implant, a fifth sidewall spacer adjacent to the first polysilicon sidewall spacer, a sixth sidewall spacer adjacent to the third polysilicon sidewall spacer, a seventh sidewall spacer adjacent to the second polysilicon sidewall spacer, and an eighth sidewall spacer adjacent to the fourth polysilicon sidewall spacer, wherein the fifth, sixth, seventh, and eighth sidewall spacers function as masks for the source/drain implant.

14. The method of claim 1 , wherein the step of forming a layer of nanocrystals is further characterized as forming a layer of tunnel oxide under the nanocrystals and a layer of control dielectric over the nanocrystals.

15. A method of forming a non-volatile memory cell having a control gate over a nanocrystal layer, a select gate, a source, and a drain, comprising:

forming a sacrificial structure over a substrate,

forming a first sidewall spacer as one of a group consisting of the select gate and control gate adjacent to a first side of the sacrificial structure;

removing the sacrificial structure;

forming a second sidewall spacer adjacent to and insulated from a first side of the first sidewall spacer functioning as one of group, different from the first sidewall spacer, consisting of the select gate and the control gate;

forming a nanocrystal layer at a location that is under one of a group consisting of the first sidewall spacer and the second sidewall spacer; and

implanting, using the first and second sidewall spacers as masks, to form the source and the drain.

16. The method of claim 15 , wherein the step of forming the second sidewall spacer comprises:

forming a layer of polysilicon;

patterning the layer of polysilicon to remove a portion of the layer of polysilicon, wherein the portion is adjacent to a second side of the first sidewall spacer; and

performing an anisotropic etch of the layer of polysilicon after the step of patterning.

17. The method of claim 16 , further comprising:

forming a dielectric layer on the substrate prior to forming the sacrificial structure;

performing a threshold adjust implant through the dielectric layer after removing the sacrificial structure;

removing the dielectric layer; and

forming a gate dielectric layer, wherein the gate dielectric layer is under the second sidewall spacer.

18. A method of forming a memory device structure, comprising:

providing a substrate;

forming a sacrificial structure over the substrate,

forming a first sidewall spacer of polysilicon of a first height adjacent to the sacrificial structure;

removing the sacrificial structure;

forming a second sidewall spacer of polysilicon adjacent to and insulated from a first side of the first sidewall spacer of a second height lower than the first height; and

forming a nanocrystal layer over the substrate at a time comprising one of a group consisting of a time before forming the first sidewall spacer and a time between the removing the sacrificial structure and the forming the second sidewall spacer.

19. The split gate memory cell of claim 18 , further comprising forming a first silicide region on a top portion of the first sidewall spacer and a second silicide region on a top portion of the second sidewall spacer.

20. The method of claim 19 further comprising:

forming a third sidewall spacer, which is a dielectric, adjacent to the first sidewall spacer;

forming a fourth sidewall spacer, which is a dielectric, adjacent to the second sidewall spacer; and

performing a source/drain implant using the first, second, third, and fourth sidewall spacers as masks.

Assignments (16)