IP Library Granted Patent US 7,702,989
Granted Patent B2
US 7,702,989 · App. 11/535,540 · Granted Apr 20, 2010

Systems and methods for generating erasure flags

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,702,989
App. No.
11/535,540
Granted
Apr 20, 2010
Kind
B2
Abstract

Various systems and methods for generating error indications are disclosed herein. In some cases, the error indication is used as an erasure pointer in a memory access system. As one particular example, a system for generating an erasure pointer is disclosed that includes accumulating a number of error values into an overall error value, and comparing the overall error value to an error threshold. When the overall error value exceeds the error threshold, an erasure pointer is generated. In one particular case, the error values are derived from a look up table using thermometer codes generated by an analog to digital converter. In other cases, the error values are derived from comparing a soft output with a reliability threshold.

Claims (33)

1. A system for generating error indications, the system comprising:

a soft output decoder, wherein the soft output decoder is operable to receive a data stream and to produce a series of soft outputs and corresponding bit decisions based on the data stream;

a reliability threshold register, wherein the reliability threshold register is operable to store a reliability threshold output;

a comparator, wherein the comparator is operable to compare the reliability threshold output with each of the respective soft outputs, and wherein the comparator is operable to provide a non-zero value each time one of the soft outputs exceeds the reliability threshold output; and

an accumulator, wherein the accumulator sums the non-zero values.

2. The system of claim 1 , wherein the comparator is a first comparator, wherein the accumulator provides an accumulator error output, and wherein the system further comprises:

an error threshold register, wherein the error threshold register provides an error threshold output; and

a second comparator, wherein the second comparator compares the error threshold output with the accumulator error output, and wherein the second comparator indicates an error condition when the accumulator error output is greater than the error threshold output.

3. The system of claim 2 , wherein the system further comprises:

a latch, wherein the latch stores the indication of the error condition.

4. The system of claim 2 , wherein an erasure pointer is asserted when the error condition is indicated.

5. The system of claim 2 , wherein the erasure pointer is asserted when both the error condition is indicated and synchronized to a symbol that corresponds to the error condition.

6. The system of claim 3 , wherein the series of reliability indicators are associated with bits of a series of symbols, and wherein the latch is updated after each of the series of symbols is identified.

7. The system of claim 6 , wherein the system further comprises:

a sync detector, and wherein the series of symbols are identified based on an output of the sync detector.

8. The system of claim 1 , wherein the soft output decoder is a soft output viterbi algorithm detector.

9. The system of claim 1 , wherein the series of soft outputs and corresponding bit decisions is a series of log likelihood ratios and corresponding bit decisions.

10. A method for generating erasure pointers, the method comprising:

receiving a data stream at a soft output decoder, wherein the soft output decoder is operable to produce a series of soft outputs and corresponding bit decisions based on the data stream;

comparing each of the series of soft outputs with a reliability threshold; and

incrementing an error value each time one of the series of soft outputs exceeds the reliability threshold.

11. The method of claim 10 , wherein the method further comprises:

comparing the error value with an error threshold; and

generating an error indication where the error value exceeds the error threshold.

12. The method of claim 11 , wherein the method further comprises:

setting the reliability threshold; and

setting the error threshold.

13. The method of claim 11 , wherein the method further comprises:

storing the error indication.

14. The method of claim 11 , wherein the series of reliability indicators are associated with bits of a series of symbols, and wherein the error indication is stored after each of the series of symbols is identified.

15. The method of claim 10 , wherein the series of soft outputs and corresponding bit decisions is a series of log likelihood ratios and corresponding bit decisions.

16. The method of claim 10 , wherein the method further comprises:

asserting an erasure pointer based on the error indication and synchronized to a symbol that corresponds to the error condition.

Assignments (11)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE PROPERTY NUMBERS PREVIOUSLY RECORDED AT REEL: 47630 FRAME: 344. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 21, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0267 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 9/5/2018 PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0687. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0344 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0687 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
CERTIFICATE OF CONVERSION Recorded Aug 29, 2014
From: AGERE SYSTEMS INC.
To: AGERE SYSTEMS LLC
Reel/Frame 033663/0948 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 17, 2007
From: GRAEF, NILS; HARATSCH, ERICH F.
To: AGERE SYSTEMS INC.
Reel/Frame 018766/0222 →