Powered patch panel
A powered patch panel (PPP) is disclosed that inserts power in mid-span regions of a network and provides fault-tolerance at the power supply level and the power-plane level. Information such as physical location, port status and policy enforcement information may be locally stored and utilized by a processor of the PPP to achieve network control and monitoring. A network management system and/or element management system may be provided to interface with processors of PPPs to achieve network monitoring, control and policy enforcement goals.
1. A powered patch panel comprising:
a memory that stores a control parameter;
a plurality of ports, each port configured to support a network communication connection;
a processor that configures at least one of the plurality of ports to selectively supply power to a powered device over the network communication connection based on the control parameter;
first and second power input ports, each of said first and second power input ports comprising a positive terminal and a negative terminal, power from the first power input port being combined with power from the second input port into a single power source;
a first diode connecting to either the positive or the negative terminal of the first power input port and a second diode connecting to the corresponding terminal of the second power input port, the first and second diodes connecting to a first node, and the terminals of the first and second power input ports that are not connected to the first and second diodes being connected to a second node;
an in-line current manager connecting to the first and second nodes to supply power to connected powered devices; and
an analog-to-digital converter configured to monitor voltages of the first and second power input ports and the first and second nodes, wherein the processor is configured to determine a status of power supplied to the first and second power input ports based on the voltages monitored by the analog-to-digital converter.
2. The powered patch panel of claim 1 , wherein the control parameter includes a current limit threshold, and the processor is configured to set a current limit for at least one of the plurality of ports based on the current limit threshold.
3. The powered patch panel of claim 1 , further comprising:
a first power-plane and a second power-plane, the first and second power-planes being separately powered;
a common circuit;
a port circuit, the first power-plane configured to provide power to the common circuit and the second power-plane configured to provide power to the port circuit; and
a register receiving power from the second power-plane, the common circuit communicating with the port circuit via a power isolator.
4. The powered patch panel of claim 1 , wherein the in-line current manager is connected to independent power planes serving different portions of the powered patch panel through independent fuses, and the in-line current manager is connected to the connected powered devices through one of the fuses.
5. The powered patch panel of claim 1 , further comprising:
a legacy detection support circuit; and
a switch having a first position and a second position,
wherein the legacy detection support circuit is configured to:
determine a characteristic of the powered device connected to the port based on a first current and a second current, and
measure the first current through the switch in the first position when a first test voltage is applied to the switch and measure the second current through the switch in the second position when a second test voltage is applied to the switch.
6. The powered patch panel of claim 1 , further comprising a plurality of LEDs associated with the ports, at least one of the LEDs indicating at least one of a status of the port or a value of a stored control parameter.
7. The powered patch panel of claim 1 , further comprising a common circuit and a port circuit configured to receive power from separate and isolated power planes, wherein the port circuit comprises a current manager, a power-over-Ethernet (PoE) manager, and an LED manager, each of the current manager, the PoE manager, and the LED manager comprising a state machine and registers, the state machine and registers in communication with the processor through at least one of an optical isolator or a capacitive isolator.
8. A powered patch panel comprising:
a plurality of ports, each port configured to support a network communication connection;
a common circuit that stores control parameters and controls the powered patch panel based upon the control parameters;
a port circuit that supplies power to a powered device connected to one of the ports over a network communication connection based on one or more of the control parameters;
a common circuit power-plane that provides power to the common circuit;
a port circuit power-plane that provides power to the port circuit;
a diode circuit that receives power from a power supply;
an in-line current manager that receives power from the diode circuit and provides power to the common circuit power-plane and the port circuit power-plane;
an analog-to-digital converter that monitors power received from the diode circuit and power output by the in-line current manager;
a first optical coupler that receives from the analog-to-digital converter a digital representation of at least one of a voltage received by the diode circuit from the first power supply, a voltage received by the diode circuit from the second power supply, a voltage output from the in-line current manager, or a current output from the in-line current manager and relays the digital representation to the common circuit; and
a second optical coupler that relays the control parameters to the port circuit from the common circuit.
9. The powered patch panel of claim 8 , wherein the port circuit further comprises:
a current manager that limits current flow to the powered device over the network communication connection based on a value set in a register and received from the common circuit;
a PoE manager that monitors a port to detect the presence and a characteristic of a powered device connected to the port;
an LED manager that controls an LED drive circuit to illuminate a port LED based on a value in a register and received from the common circuit; and
a legacy support manager that determines whether a powered device connected to a port is a first type of PoE device or a second type of PoE device.
10. The powered patch panel of claim 8 , wherein the common circuit further comprises:
a memory that stores the control parameters;
an Ethernet switch that supports communication between the common circuit and an Ethernet network management port; and
a processor that receives the control parameters via the Ethernet network management port and instructs the memory to store the control parameters.
11. The powered patch panel of claim 10 , wherein the Ethernet switch within the common circuit supports two Ethernet network management ports that support formation of a daisy-chain to connect multiple powered patch panels onto a single Ethernet network connection.
12. The powered patch panel of claim 8 , further comprising a capacitive coupler that relays information from the legacy support manager to a processor in the common circuit, the information pertaining to the powered device connected to the port.
13. The powered patch panel of claim 8 , further comprising:
a first fuse that connects the in-line current manager to the port circuit power-plane; and
a second fuse that connects the in-line current manager to the common circuit power-plane.