Timing error detector for vestigial side band (VSB)
The present invention provides a novel symbol timing recovery method for VSB receivers. Systems are described that comprise a timing error detector (TED) that produces an exact symbol timing error even in the presence residual carrier phase offset, loop filter that controls the characteristics of acquisition and tracking of digital PLL loop, Voltage/Numerically Controlled Oscillator (VCO/NCO) that adjusts the sampling instant and phase, A/D converter that samples a continuous VSB input signal, and a interpolating squared root raised cosine filter that performs both matched filtering and a compensation of constant timing offset of quarter symbol caused by the invented TED. The timing error detector in this invention comprises an envelope detector, band pass filter, squaring block, high pass filter, and decimator. It uses both in-phase and quadrature-phase component of received VSB signal, is operated at twice of a symbol frequency F, and guarantees consistent symbol timing error signal resulting in the improvement of receiver's performance.
1. A timing error detector for a vestigial side band (“VSB”) comprising
an envelope detector, and
an envelope processor, wherein:
the envelope detector receives a complex baseband signal derived from a VSB signal and calculates energy of the complex baseband signal; and
the envelope processor receives the energy calculation from the envelope detector and generates an error signal representative of a phase error in the complex baseband signal.
2. The timing error detector of claim 1 , wherein the envelope detector comprises a first signal squarer and the envelope processor comprises a second signal squarer.
3. The timing error detector of claim 2 , wherein the envelope processor further comprises a high pass filter.
4. The timing error detector of claim 2 , wherein the envelope processor further comprises a decimator.
5. The timing error detector of claim 1 , wherein the envelope detector performs conjugate multiplication of the complex baseband signal.
6. A method for phase independent timing error detection comprising the steps of:
digitizing a Vestigial Side Band (“VSB”) signal in a digitizer configured to sample the VSB signal at a selected sampling rate;
providing a complex baseband VSB signal, wherein providing the complex baseband VSB signal includes removing a carrier signal from the complex VSB signal and splitting the digitized VSB signal into complex components; and
generating in a timing error detector, a time error signal based on the complex VSB signal wherein the timing error detector includes an envelope detector and an envelope processor.
7. The method of claim 6 , wherein the step of providing a complex baseband signal further includes obtaining an interpolated signal between samples of the VSB signal associated with an offset determined by the time error signal.
8. The method of claim 7 , wherein the step of providing a complex baseband VSB signal occurs prior to the step of obtaining an interpolated signal.
9. The method of claim 7 , wherein the step of obtaining an interpolated signal occurs prior to the step of providing a complex baseband VSB signal.
10. The method of claim 6 , wherein the sampling rate is selected based on the time error signal.
11. The timing error detector of claim 1 , wherein the error signal includes a timing error signal generated from a complex representation of an interpolated signal.
12. The timing error detector of claim 11 , wherein the interpolated signal is representative of a Vestigial Side Band (“VSB”) signal.
13. The timing error detector of claim 11 , wherein the timing error signal is unaffected by phase offset in a carrier signal.
14. The timing error detector of claim 13 , wherein the timing error signal is unaffected by jitter in the carrier signal.
15. The timing error detector of claim 11 , wherein the timing error signal is unaffected by jitter in the carrier signal.
16. The timing error detector of claim 1 , wherein the error signal is unaffected by carrier phase offset.
17. The timing error detector of claim 1 , wherein the error signal is unaffected by jitter.
18. The timing error detector of claim 1 , wherein the error signal is unaffected by carrier phase offset and jitter.
19. The method of claim 6 , wherein generating the timing error signal includes squaring an input signal of the envelope detector.
20. The method of claim 6 , wherein generating the timing error signal includes bandpass filtering an output of the envelope detector.
21. The method of claim 20 , wherein generating the timing error signal includes squaring the bandpass filtered output.
22. The method of claim 21 , wherein generating the timing error signal includes high pass filtering and decimating the squared, bandpass filtered output.
23. The method of claim 22 , wherein generating the timing error signal includes squaring an input signal provided to the envelope detector.
24. The method of claim 6 , wherein generating the timing error signal includes a first squaring step performed in the envelope detector and a second squaring step performed in the envelope processor.