Semiconductor device and manufacturing method thereof for reducing the area of the memory cell region
View Patent ↗A structure is adopted for a layout of an SRAM cell which provides a local wiring 3 a between a gate 2 a and gate 2 b and connects an active region 1 a and an active region 1 b . This eliminates the necessity for providing a contact between the gate 2 a and the gate 2 b . Therefore, it is possible to reduce the size of a memory cell region C in a short side direction. Furthermore, a structure whereby a left end of a gate 2 c is retreated from the gate 2 a and a local wiring 3 b which connects the active region 1 b and gate 2 c disposed in a diagonal direction is adopted. This allows the gate 2 a to be shifted toward the center of the memory cell region C.
1. A method of manufacturing a semiconductor device comprising the steps of:
a step of forming a first active region and a second active region which is separated from said first active region by an element isolator and provided at a position closer to a center of said memory cell region than said first active region, in a memory cell region on a substrate;
a step of forming a first gate electrode which crosses said first active region, a second gate electrode which is separated from said first gate electrode and crosses said first active region and said second active region and a third gate electrode which is separated from said first gate electrode and said second gate electrode, an end of which is opposed to an end of said first gate electrode on said second active region side and retreated from said first gate electrode more than an end of said second active region opposed to said first gate electrode;
a step of forming a first drain section between said first gate electrode and said second gate electrode in said first active region and a second drain section at the position of the same side of said first drain toward said second gate electrode in said second active region;
a step of forming a first wiring which connects said first drain section and said second drain section; and
a step of forming a second wiring which connects said second drain section and said third gate electrode.
2. The method of manufacturing a semiconductor device according to claim 1 , wherein the step of forming said first wiring and the step of forming said second wiring are carried out simultaneously, said step comprising the steps of:
a step of forming a first insulating film on said substrate;
a step of forming a first groove and a second groove by selectively etching said first insulating film; and
a step of forming said first wiring in said first groove and forming said second wiring in said second groove.
3. The method of manufacturing a semiconductor device according to claim 1 , wherein the step of forming said first wiring comprises the steps of:
a step of forming a first insulating film on said substrate;
a step of selectively etching said first insulating film to form a first groove; and
a step of forming said first wiring in said first groove, and
the step of forming said second wiring comprises:
a step of forming a second insulating film on said substrate and said first wiring;
a step of forming a second groove by selectively etching said second insulating film and said first insulating film; and
a step of forming said second wiring in said second groove.
4. A method of manufacturing a semiconductor device comprising the steps of:
a step of forming a first active region and a second active region which is separated from said first active region by an element isolator and provided at a position closer to a center of said memory cell region than said first active region, in a memory cell region on a substrate;
a step of forming a groove by selectively etching a surface of the element isolator between said first active region and said second active region;
a step of forming a first wiring which connects said first active region and said second active region in said groove;
a step of forming a first gate electrode which is separated from said first wiring and crosses said first active region, a second gate electrode which is separated from said first gate electrode and said first wiring and crosses said first active region and said second active region opposite said first gate electrode with said first wiring placed in between and a third gate electrode which is separated from said first gate electrode, said second gate electrode and said first wiring, an end of which is opposed to an end of said first gate electrode on said second active region side and retreated from said first gate electrode more than an end of said second active region opposed to said first gate electrode; and
a step of forming a first drain section between said first gate electrode and said second gate electrode in said first active region and a second drain section at the position of the same side of said first drain toward said second gate electrode in said second active region.