Wiring structure and method of semiconductor integrated circuit
View Patent ↗To provide wiring structure and method capable of supplying a scan clock signal for each clock domain without requesting a user to add a test circuit. The wiring structure of a semiconductor integrated circuit according to an embodiment of the present invention includes: a fixed layer where a common line independent of a user circuit is formed; and a customized layer which is formed on the fixed layer and in which a line dependent on the user circuit is formed. The fixed layer is provided with a scan clock line supplying a scan clock signal for scan test to the selecting circuit, and a clock line supplying an output signal of the selecting circuit to a flip-flop of a scan path, and the customized layer is provided with a user clock line supplying a user clock signal to the selecting circuit.
1. A wiring structure of a semiconductor integrated circuit, comprising:
a fixed layer where a common line independent of a user circuit and a basic cell including a selecting circuit are formed; and
a customized layer which is formed on the fixed layer and in which a line dependent on the user circuit is formed,
the fixed layer being provided with a scan clock line supplying a scan clock signal for scan test to the selecting circuit, and a clock line supplying an output signal of the selecting circuit to a circuit of a scan path, and
the customized layer is provided with a user clock line supplying a user clock signal to the selecting circuit.
2. The wiring structure of a semiconductor integrated circuit according to claim 1 , wherein the selecting circuit and the clock line are provided for each clock domain.
3. The wiring structure of a semiconductor integrated circuit according to claim 2 , wherein the scan clock line is provided for each selecting circuit in a one-to-one relationship.
4. The wiring structure of a semiconductor integrated circuit according to claim 1 , wherein the user clock line supplies a user clock signal to the selecting circuit through a PLL circuit or a gating circuit.
5. The wiring structure of a semiconductor integrated circuit according to claim 1 , wherein a line supplying a user clock signal input from the user clock line to a plurality of the selecting circuits is formed in the fixed layer.
6. The wiring structure of a semiconductor integrated circuit according to claim 1 , wherein a line supplying a plurality of user clock signals different in at least one of a phase and a frequency output from a PLL circuit that receives a user clock signal from the user clock line to generate the plurality of user clock signals, to a plurality of the selecting circuits through a clock selecting circuit, is formed in the fixed layer.
7. A wiring method of a semiconductor integrated circuit including: a fixed layer where a common line independent of a user circuit and a basic cell including a selecting circuit are formed; and a customized layer which is formed on the fixed layer and in which a line dependent on the user circuit is formed, comprising:
forming a scan clock line supplying a scan clock signal for scan test to the selecting circuit, and a clock line supplying an output signal of the selecting circuit to a circuit of a scan path in the fixed layer; and
forming a user clock line supplying a user clock signal to the selecting circuit in the customized layer.
8. The wiring method of a semiconductor integrated circuit according to claim 7 , wherein the selecting circuit and the clock line are provided for each clock domain.
9. The wiring method of a semiconductor integrated circuit according to claim 8 , wherein the scan clock line is provided for each selecting circuit in a one-to-one relationship.
10. The wiring method of a semiconductor integrated circuit according to claim 7 , wherein the user clock line supplies a user clock signal to the selecting circuit through a PLL circuit or a gating circuit.
11. The wiring method of a semiconductor integrated circuit according to claim 7 , wherein a line supplying a user clock signal input from the user clock line to a plurality of the selecting circuits is formed in the fixed layer.
12. The wiring method of a semiconductor integrated circuit according to claim 7 , wherein a line supplying a plurality of user clock signals different in at least one of a phase and a frequency output from a PLL circuit that receives a user clock signal from the user clock line to generate the plurality of user clock signals, to a plurality of the selecting circuits through a clock selecting circuit, is formed in the fixed layer.