Semiconductor device with stress reducing trench fill containing semiconductor microparticles in shallow trench isolation
View Patent ↗A semiconductor device includes: a semiconductor substrate formed with an active region and an isolation region and having a trench formed in the isolation region; an isolation insulating film embedded in the trench of the semiconductor substrate; and semiconductor nanocrystals buried in the isolation insulating film. The coefficient of linear expansion of the semiconductor nanocrystal is closer to that of the semiconductor substrate rather than that of the isolation insulating film, so that stress applied to the active region after a thermal treatment or the like is reduced.
1. A semiconductor device which comprises a first isolation region formed in a semiconductor substrate,
wherein a first trench surrounding a first active region of the semiconductor substrate and a first insulating film embedded in the first trench are formed in the first isolation region, and
the first insulating film contains semiconductor microparticles made of a group IV semiconductor crystal and at least either of a p-type impurity and an n-type impurity.
2. The device of claim 1 ,
wherein the semiconductor microparticles are present only in a region of the first insulating film.
3. The device of claim 1 ,
wherein the first insulating film comprises:
a lower insulating film covering an inner wall of the first trench and containing the semiconductor microparticles; and
an upper insulating film provided on the lower insulating film and filling the first trench.
4. The device of claim 1 , further comprising an impurity diffusion layer formed in the first active region,
wherein the first trench in the first isolation region is formed to have a greater depth from the surface of the semiconductor substrate than the impurity diffusion layer, and
the semiconductor microparticles within the first insulating film are present in a region thereof located more shallowly than the deepest portion of the impurity diffusion layer in the depth direction from the surface of the semiconductor substrate.
5. The device of claim 1 , further comprising, in the semiconductor substrate, a second isolation region in which a second trench surrounding a second active region of the semiconductor substrate and a second insulating film embedded in the second trench are formed,
wherein the second insulating film does not contain the semiconductor microparticles.
6. The device of claim 5 , further comprising:
an n-channel MIS transistor formed on the first active region; and
a p-channel MIS transistor formed on the second active region.
7. The device of claim 5 , further comprising:
a p-channel MIS transistor formed on the first active region; and
an n-channel MIS transistor formed on the second active region.
8. The device of claim 6 ,
wherein the n-channel MIS transistor has a finger length of 0.3 μm or smaller.
9. The device of claim 7 ,
wherein the p-channel MIS transistor has a finger length of 0.4 μm or smaller.
10. The device of claim 1 ,
wherein the semiconductor microparticles are made of one material selected from a silicon crystal, a germanium crystal, and a silicon germanium crystal.
11. The device of claim 1 ,
wherein the semiconductor microparticles within the first insulating film are spaced 1.5 nm or more away from each other.
12. A semiconductor device which comprises a first isolation region formed in a semiconductor substrate,
wherein a first trench surrounding a first active region of the semiconductor substrate and a first insulating film embedded in the first trench are formed in the first isolation region,
the first insulating film contains semiconductor microparticles made of a group IV semiconductor crystal,
the device further comprises an impurity diffusion layer formed in the first active region,
wherein the first trench in the first isolation region is formed to have a greater depth from the surface of the semiconductor substrate than the impurity diffusion layer, and
the semiconductor microparticles within the first insulating film are present in a region thereof located more shallowly than the deepest portion of the impurity diffusion layer in the depth direction from the surface of the semiconductor substrate.
13. A semiconductor device which comprises a first isolation region formed in a semiconductor substrate,
wherein a first trench surrounding a first active region of the semiconductor substrate and a first insulating film embedded in the first trench are formed in the first isolation region,
the first insulating film contains semiconductor microparticles made of a group IV semiconductor crystal,
the device further comprises in the semiconductor substrate, a second isolation region in which a second trench surrounding a second active region of the semiconductor substrate and a second insulating film embedded in the second trench are formed, and
wherein the second insulating film does not contain the semiconductor microparticles.
14. The device of claim 13 , further comprising:
an n-channel MIS transistor formed on the first active region; and
a p-channel MIS transistor formed on the second active region.
15. The device of claim 13 , further comprising:
a p-channel MIS transistor formed on the first active region; and
an n-channel MIS transistor formed on the second active region.
16. The device of claim 14 ,
wherein the n-channel MIS transistor has a finger length of 0.3 μm or smaller.
17. The device of claim 15 ,
wherein the p-channel MIS transistor has a finger length of 0.4 μm or smaller.
18. The device of claim 13 ,
wherein the semiconductor microparticles are made of one material selected from a silicon crystal, a germanium crystal, and a silicon germanium crystal.
19. The device of claim 13 ,
wherein the semiconductor microparticles within the first insulating film are spaced 1.5 nm or more away from each other.