Semiconductor devices and manufacturing methods of the same
View Patent ↗A semiconductor device may include first and second silicon layers formed over a semiconductor substrate. An insulating layer may be formed between first and second silicon layers. A gate insulating layer, a gate electrode, and a spacer may be formed over a second silicon layer. A source/drain impurity area may be formed over a second silicon layer on both sides of a gate electrode.
1. A semiconductor device comprising:
a first strained silicon layer and a second strained silicon layer formed over a semiconductor substrate;
a first insulating layer formed between the first strained silicon layer and the second strained silicon layer;
a gate insulating layer, a gate electrode, and a spacer sequentially formed over the second strained silicon layer; and
a source/drain impurity area formed in the second strained silicon layer on both sides of the gate electrode.
2. The semiconductor device of claim 1 , wherein the first and second strained silicon have grid spacing different from unstrained silicon.
3. The semiconductor device of claim 1 , wherein the first strained silicon layer comprises silicon that is strained using germanium.
4. The semiconductor device of claim 1 , wherein the first insulating layer comprises an oxide layer.
5. The semiconductor device of claim 1 , wherein the first insulating layer comprises a nitride layer.
6. The semiconductor device of claim 1 , wherein the first insulating layer is formed below the gate electrode.
7. The semiconductor device of claim 1 , wherein the first insulating layer is formed in a trench and the trench is formed in the first strained silicon layer.
8. A method for manufacturing a semiconductor device comprising:
forming a first strained silicon layer over a semiconductor substrate;
forming a trench in the first strained silicon layer;
forming a first insulating layer over the trench;
forming a second strained silicon layer over the first strained silicon layer and over the first insulating layer; and
forming a gate insulating layer and a pate electrode over the second strained silicon layer;
forming a lightly doped drain area in the second strained silicon layer by implanting dopants;
forming a spacer on both sides of the gate electrode; and
forming a source/drain area by implanting dopants.
9. The method of claim 8 , wherein the first strained silicon layer is formed by growing germanium on the semiconductor substrate through an epitaxial process.
10. The method of claim 8 , wherein said forming the first insulating layer comprises:
forming the first insulating layer over the first strained silicon layer having the trench; and
performing a chemical mechanical polishing process on the first strained silicon layer and the first insulating layer.
11. The method of claim 8 , wherein the first and second strained silicon layers comprise strained silicon having grid spacing different from unstrained silicon.
12. The method of claim 8 , wherein the first strained silicon layer comprises silicon that is strained using germanium.
13. The method of claim 8 , wherein the first insulating layer comprises an oxide layer.
14. The method of claim 8 , wherein the first insulating layer comprises a nitride layer.
15. The method of claim 8 , wherein the first insulating layer is formed below the gate electrode.
16. The method of claim 8 , wherein the second strained silicon layer directly contacts the first strained silicon layer and the first insulating layer.
17. The semiconductor device of claim 1 , wherein the second strained silicon layer directly contacts the first strained silicon layer and the first insulating layer.
18. The semiconductor device of claim 1 , wherein the first insulating layer is coplanar with the first strained silicon layer.