Direct digital interpolative synthesis

1. An apparatus comprising:

a fractional-N divider configured to receive a signal and supply a divided signal divided in accordance with a divide control signal;

a delta sigma modulator coupled to receive a divide ratio and generate an integer portion and a digital quantization error and to supply the integer portion as the divide control signal to the fractional-N divider; and

a phase interpolator coupled to the fractional-N divider and to the delta sigma modulator to adjust a phase of the divided signal according to the digital quantization error to reduce error in the divided signal.

2. The apparatus as recited in claim 1 further comprising a voltage controlled oscillator coupled to supply the fractional-N divider with the signal.

3. The apparatus as recited in claim 1 further comprising digital skew control logic to supply a digital skew control signal supplied to the delta sigma modulator to provide spread spectrum modulation of the divided signal.

4. The apparatus as recited in claim 2 further comprising a phase-locked loop including the VCO.

5. The apparatus as recited in claim 4 wherein the phase-locked loop includes a feedback divider, and the feedback divider includes a phase interpolator controlled by a digital quantization error of a second delta sigma modulator.

6. The apparatus as recited in claim 4 wherein the phase-locked loop comprises:

a feedback divider, the feedback divider being an interpolative divider including,

a second fractional-N divider coupled to receive a feedback signal and to supply a divided feedback signal divided in accordance with a second divide control value;

a second delta sigma modulator coupled to receive another divide ratio and generate a second integer portion and a second digital quantization error and to supply the second integer portion as the second divide control signal to the second fractional-N divider; and

a second phase interpolator coupled to the second fractional-N divider and to the second delta sigma modulator to adjust a phase of the divided feedback signal according to the second digital quantization error to reduce error in the divided feedback signal.

7. The apparatus as recited in claim 4 further comprising a fixed frequency source coupled to supply the phase-locked loop.

8. The apparatus as recited in claim 7 wherein the fixed frequency source is one of a crystal oscillator and a MEMS oscillator.

9. The apparatus as recited in claim 1 further comprising a non-volatile memory coupled to the delta sigma modulator to supply the divide ratio.

10. The apparatus as recited in claim 1 further comprising a free running oscillator supplying the signal to the fractional-N divider.

11. The apparatus as recited in claim 10 further comprising a temperature compensation circuit coupled to adjust the divide ratio according to the detected temperature.

12. A method comprising:

receiving a divide ratio in a delta sigma modulator and generating an integer portion and a digital quantization error corresponding to the divide ratio and supplying the integer portion as a divide value to a fractional-N divider;

dividing a signal in the fractional-N divider according to the divide value and generating a divided signal; and

adjusting a phase of the divided signal in a phase interpolator coupled to the fractional-N divider according to the digital quantization error to reduce error in the divided signal.

13. The method as recited in claim 12 further comprising supplying the signal to the fractional-N divider from a voltage controlled oscillator.

14. The method as recited in claim 12 further comprising supplying a digital skew control signal to the delta sigma modulator to provide spread spectrum modulation.

15. The method as recited in claim 13 further comprising:

supplying the signal from a phase-locked loop including a voltage controlled oscillator (VCO); and

dividing a feedback signal from the VCO in a divider circuit of the phase-locked loop.

16. The method as recited in claim 15 further comprising:

dividing the feedback signal in another fractional-N divider according to a feedback divide control signal corresponding to an integer portion of a feedback divide ratio; and

adjusting a phase of the divided feedback signal in a phase interpolator according to a fractional portion of the feedback divide ratio corresponding to a digital quantization error of a second delta sigma modulator.

17. The method as recited in claim 15 further comprising supplying a phase and frequency detector of the phase-locked loop with a signal from a fixed frequency source coupled to the phase-locked loop.

18. The method as recited in claim 12 further comprising supplying the divide ratio from a non-volatile memory coupled to the delta sigma modulator.

19. A clock synthesis apparatus comprising:

means for providing a divided signal corresponding to an integer portion of divide a divide ratio; and

means for adjusting a phase of the divided signal according to a digital quantization error corresponding to a fractional portion of the divide ratio.

20. A method comprising reducing error in an output signal of a divider circuit by adjusting the output signal in a phase interpolator according to a quantization error generated in determining control values for the divider circuit.

21. The method as recited in claim 20 further comprising supplying the divider circuit with a signal to divide from a free running oscillator.

22. An apparatus comprising:

a divider circuit coupled to receive a signal and supply a divided signal according to a sequence of divide values supplied by a divide control circuit; and

a phase interpolation circuit coupled to the divide circuit to adjust the divided signal according to a quantization error generated by the divide control circuit in determining the divide values.

23. The apparatus as recited in claim 22 wherein the divide control circuit is a delta sigma modulator coupled to receive a divide ratio and generate an integer portion as the divide values and the quantization error.