Patent Assignment
Reel/Frame 057033/0579
Assignment of Assignor's Interest
Recorded: 2021-07-29
Pages: 56
Assignor
SILICON LABORATORIES INC.
Executed: 2021-07-23
Assignee
SKYWORKS SOLUTIONS, INC.
5260 CALIFORNIA AVENUE, IRVINE, CALIFORNIA, 92617
Covered Properties
(427)
Method and Apparatus for a Programmable Clock Source Generating a Wide Range of Output Frequencies
PCT:
PCT/US2004/013780 ↗
Spread Spectrum Isolator
PCT:
PCT/US2005/019313 ↗
Integrated Low-If Terrestrial Audio Broadcast Receiver and Associated Method
PCT:
PCT/US2005/022398 ↗
Local Oscillator and Mixer for a Transceiver
PCT:
PCT/US2005/025171 ↗
Data Cleaning with an Asynchronous Reference Clock
PCT:
PCT/US2006/010414 ↗
Television Receiver with Automatic Gain Control (Agc)
PCT:
PCT/US2006/011792 ↗
System and Method for Voltage Protection in a Powered Device
PCT:
PCT/US2007/015416 ↗
System and Method for Selecting Channels for Short Range Transmissions to Broadcast Receivers
PCT:
PCT/US2007/017946 ↗
Integrating an Fm Transmitter into a Cellular Telephone
PCT:
PCT/US2007/020504 ↗
Harmonic Rejection Mixer
PCT:
PCT/US2007/020505 ↗
Performing a Coordinate Rotation Digital Computer (Cordic) Operation for Amplitude Modulation (Am) Demodulation
PCT:
PCT/US2007/020564 ↗
Voltage Protection Circuit for Power Supply Device and Method Therefor
PCT:
PCT/US2007/023480 ↗
Direct Digital Interpolative Synthesis
PCT:
PCT/US2007/079410 ↗
A Rotating Harmonic Rejection Mixer
PCT:
PCT/US2008/068312 ↗
An Antenna for Use in Portable Applications
PCT:
PCT/US2008/068326 ↗
Combining Multiple Frequency Modulation (Fm) Signals in a Receiver
PCT:
PCT/US2009/044759 ↗
Circuit Device and Method of Current Limit-Based Disconnect Detection
PCT:
PCT/US2009/058193 ↗
Surge Protection for a Data Access Arrangement
Patent:
6,876,742 →
Application:
09/676,742 →
Differential Mode Circuitry and Method of Calibrating Same Without Matched External Current Sources
Method and Apparatus for Acquiring a Frequency Without a Reference Clock
Patent:
6,856,206 →
Application:
09/888,663 →
Clock and Data Recovery Circuit Without Jitter Peaking
Patent:
7,227,913 →
Application:
09/888,717 →
Digitally-Synthesized Loop Filter Circuit Particularly Useful for a Phase Locked Loop
Digital Phase Detector Circuit and Method Therefor
Integrated Circuit Incorporating Circuitry for Determining Which of at Least Two Possible Frequencies Is Present on an Externally Provided Reference Signal and Method Therefor
Patent:
6,686,803 →
Application:
09/902,543 →
Apparatus and Method for Decimating a Digital Input Signal
Use of Dual Hysteresis Modes in Determining a Loss of Signal Output Indication
Patent:
6,489,803 →
Application:
09/949,483 →
Serial Device Daisy Chaining Method and Apparatus
Offset Correction and Slicing Level Adjustment for Amplifier Circuits
Patent:
6,657,488 →
Application:
10/036,986 →
Digital-To-Analog Converter Switching Circuitry
Auto-Detection Between Referenceless and Reference Clock Mode of Operation
Patent:
6,831,523 →
Application:
10/131,002 →
Method and Apparatus for Adjusting the Phase of an Output of a Phase-Locked Loop
Patent:
6,920,622 →
Application:
10/187,937 →
Method and Apparatus for Generating a Clock Signal in Holdover Mode
Patent:
7,148,753 →
Application:
10/453,990 →
Digitally-Synthesized Loop Filter Circuit Particularly Useful for a Phase Locked Loop
Digital-To-Analog Converter Switching Circuitry
Reconfigurable terminal
Application:
10/675,529 →
Publication:
US 2005/0068118
Calibration of Oscillator Devices
Dual Phased-Locked Loop Structure Having Configurable Intermediate Frequency and Reduced Susceptibility to Interference
Patent:
6,970,030 →
Application:
10/676,626 →
Low-Noise Block Controller Within a Set-Top Box
Electromagnetic Shielding Structure
Transformer Isolator for Digital Power Supply
On Chip Transformer Isolator
Communication Devices Capable of Using System Clock Inputs for Embedded Television Applications
Voltage Reference Generator Circuit Subtracting Ctat Current from Ptat Current
Phase Error Cancellation
Method and Apparatus for Temperature Compensation
Multiple Signal Format Output Buffer
Phase Selectable Divider Circuit
Dual Loop Architecture Useful for a Programmable Clock Source and Clock Multiplier Applications
Integrated Low-If Terrestrial Audio Broadcast Receiver and Associated Method
Digitally-Synthesized Loop Filter Method and Circuit Particularly Useful for a Phase Locked Loop
Local Oscillator and Mixer for Transceiver
Delta-Sigma Modulator with Selectable Noise Transfer Function
Hybrid Analog/Digital Phase Lock Loop Frequency Synthesizer
Patent:
7,084,709 →
Application:
10/993,592 →
Method and Apparatus for Noise Compensation in an Oscillator Circuit
Rf Isolator with Differential Input/Output
Reducing Phase Offsets in a Phase Detector
Calibrating a Phase Detector and Analog-to-Digital Converter Offset and Gain
Method and Apparatus for a Hybrid Phase Lock Loop Frequency Synthesizer
Patent:
7,180,377 →
Application:
11/039,113 →
Method and Apparatus for Acquiring a Frequency Without a Reference Clock
Rf Isolator for Isolating Voltage Sensing and Gate Drivers
On-Chip Calibration Signal Generation for Tunable Filters for Rf Communications and Associated Methods
Spread Spectrum Isolator
Television receiver with automatic gain control (AGC)
Application:
11/093,547 →
Publication:
US 2006/0222115
Data Cleaning with an Asynchronous Reference Clock
Phase Adjustment for a Divider Circuit
Signal Dependent Biasing Scheme for an Amplifier
Utilization of Device Types Having Different Threshold Voltages
Selectably Boosted Control Signal Based on Supply Voltage
Configurable Circuit Structure Having Reduced Susceptibility to Interference When Using at Least Two Such Circuits to Perform Like Functions
Output Driver with Common Mode Feedback
Cancellation of Undesired Portions of Audio Signals
Multi-Frequency Clock Synthesizer
Voltage Controlled Clock Synthesizer
Expanded Pull Range for a Voltage Controlled Clock Synthesizer
Input Buffer
Dual Antenna Communications Device
System and method for high voltage protection of powered devices
Application:
11/433,221 →
Publication:
US 2007/0263332
System and Method of Detection of Power Loss in Powered Ethernet Devices
Output Stacking Architecture for an Amplifier
Robust False Locking Prevention in Referenceless Frequency Acquisition
System and Method of Classification in Power Over Ethernet Systems
System and Method for High Voltage Protection of Powered Devices
Powered Device Including a Classification Signature Resistor
Voltage Protection System and Method for a Powered Device
System and Method of Surge Protection in a Powered Device
Powered Device Including a Detection Signature Resistor
Integrated Circuit Including a Switching Regulator Design for Power Over Ethernet Devices
System and Method for Selecting Channels for Short Range Transmissions to Broadcast Receivers
Harmonic Rejection Mixer
Integrating an Fm Transmitter into a Cellular Telephone
Television Reciever with Automatic Gain Control (Agc)
Performing a Coordinate Rotation Digital Computer (Cordic) Operation for Amplitude Modulation (Am) Demodulation
Adaptive Asynchronous Sample Rate Conversion
Patent:
7,339,503 →
Application:
11/536,841 →
Communications Device with Asynchronous Sample Rate Converter
Patent:
7,339,504 →
Application:
11/536,852 →
Technique for Switching Between Input Clocks in a Phase-Locked Loop
Direct Digital Interpolative Synthesis
Programmable Phase-Locked Loop Responsive to a Selected Bandwidth and a Selected Reference Clock Signal Frequency to Adjust Circuit Characteristics
Phase Error Cancellation
Providing Channel Filtering in an Automatic Frequency Control Path
Powered device including a detection signature circuit
Voltage Protection Circuit for Power Supply Device and Method Therefor
Digital Hold in a Phase-Locked Loop
High-Speed Divider with Reduced Power Consumption
High-Speed Divider with Pulse-Width Control
Calibration of Oscillator Devices
Application:
11/681,941 →
Publication:
US 2007/0146083
Integrated Low-If Terrestrial Audio Broadcast Receiver and Associated Method
Receiver Architectures for Digital Radio Broadcasts and Associated Methods
Apparatus Having Integrated Radio and Gps Receivers
Transformer Coils for Providing Voltage Isolation
Multiplexed Rf Isolator
Bidirectional Multiplexed Rf Isolator
Multiplexed Rf Isolator Circuit
Antenna for Use in Portable Applications
Rotating Harmonic Rejection Mixer
Method and Apparatus for Controlling a Harmonic Rejection Mixer
System and Method for Transmitting Rds/Rbds Data
Integrated Low-If Terrestrial Audio Broadcast Receiver and Associated Method
Variable Sense Level for Fuse-Based Non-Volatile Memory
Patent:
7,742,352 →
Application:
11/927,845 →
Spread Spectrum Isolator
Circuit Device and Method of Providing Feedback Across an Isolation Barrier
Circuit Device and Method of Supressing a Power Event
System and Method of Classification in Power Over Ethernet Systems
Capacitive Isolator
Power Supply with Digital Control Loop
Digital Interface for Tuner-Demodulator Communications
Power Sourcing Equipment Device Including a Serial Interface
Isolator Circuit Including a Voltage Regulator
On Chip Transformer Isolator
Combining Multiple Frequency Modulation (Fm) Signals in a Receiver
System and Method of Providing Electrical Isolation
System and Method of Providing Electrical Isolation
Mcu with Integrated Voltage Isolator to Provide a Galvanic Isolation Between Input and Output
Mcu with Integrated Voltage Isolator and Integrated Galvanically Isolated Asynchronous Serial Data Link
Direct Digital Interpolative Synthesis
Powered Device Including a Multi-Use Detection Resistor
Mechanical Tuning of a Radio
Frequency Adjustment for Clock Generator
Circuit Device and Method of Current Limit-Based Disconnect Detection
Circuit Device to Generate a High Precision Control Signal
Dual Loop Architecture Useful for a Programmable Clock Source and Clock Multiplier Applications
Methods and Systems for Stereo Noise Mitigation
Integrated Air Loop Antenna and Transformer Antenna Assembly
Low-Cost Receiver Using Automatic Gain Control
Capacitive Isolation Circuitry
Capacitive Isolation Circuitry with Improved Common Mode Detector
Low-If Integrated Data Receiver and Associated Methods
Low-Noise Amplifier Suitable for Use in a Television Receiver
Digital Signal Processor (DSP) Architecture For A Hybrid Television Tuner
Isolator with Complementary Configurable Memory
Schmitt Trigger with Gated Transition Level Control
Electronic Timer System, Time Control and Generation of Timing Signals
Digital Phase Lock Loop Configurable as a Frequency Estimator
Calibrating a Phase Detector and Analog-to-Digital Converter Offset and Gain
Successive Approximation Register (Sar) Analog-to-Digital Converter (Adc) Having Optimized Filter
Radio Receiver Having a Multipath Equalizer
Mechanically tuned radio utilizing ratiometric time measurements and related methods
Method and System for Fm Tuner Ground Isolation When Using Ground Signal Line as Fm Antenna
Systems and Methods for Controlling Integrated Circuit Operation with Below Ground Pin Voltage
Digital Signal Processor (Dsp) Architecture for a Hybrid Television Tuner
Mitigating Radio Receiver Multipath Noise
System and Method of Classification in Power Over Ethernet Systems
Configurable Radio Front End
Antenna Diversity System with Frame Synchronization
Tuner Circuit with an Inter-Chip Transmitter and Method of Providing an Inter-Chip Link Frame
Application:
12/649,911 →
Publication:
US 2011/0158298
Antenna Diversity System with Multiple Tuner Circuits Having Multiple Operating Modes and Methods
Spread Spectrum Isolator
Implementing a Rotating Harmonic Rejection Mixer (Rhrm) for a Tv Tuner in an Integrated Circuit
Multi-Standard Digital Demodulator for Tv Signals Broadcast Over Cable, Satellite and Terrestrial Networks
Reducing Power Consumption in an Iterative Decoder
Techniques to Control Power Consumption in an Iterative Decoder by Control of Node Configurations
Buffer with an Output Swing Created Using an Over-Supply Voltage
Mismatch-Immune Digital-to-Analog Converter
Performing Impulse Blanking Based on Blocker Information
Rotating Harmonic Rejection Mixer
Methods and Systems for Blending Between Stereo and Mono in a Fm Receiver
System and Method of Classification in Power Over Ethernet Systems
Power Sourcing Equipment Device Including a Serial Interface
Subscriber Line Interface Circuit with Intra-Operational State Selectable Supply
Voltage Controlled Oscillator with Dither
Controlling Power Consumption In A Radio Tuner
Direct Digital Interpolative Synthesis
Method And Apparatus For Controlling A Harmonic Rejection Mixer
Capacitive Isolator with Schmitt Trigger
Oscillator with External Voltage Control and Interpolative Divider in the Output Path
Receiver and Method of Receiving Analog and Digital Television Signals
A Timer System for Maintaining the Accuracy of a Real Time Clock When Synchronization Source Is Not Available
Receiver Circuits and Systems for Receiving Medium Wave and Short Wave Signals
Application:
13/007,572 →
Publication:
US 2012/0183102
Rotating Harmonic Rejection Mixer
Low Noise Amplifier (Lna) Suitable for Use in Different Transmission Environments and Receiver Using Such an Lna
Compensation for Crystal Offset in Pll-Based Crystal Oscillators
Patent:
8,242,849 →
Application:
13/076,081 →
Transition Interval Coding for Serial Communication
Receiver Architectures for Digital Radio Broadcasts and Associated Methods
Providing Channel Filtering In An Automatic Frequency Control Path
Providing Phase Diversity Combining Of Digital Radio Broadcast Signals
Dynamic Time Alignment of Audio Signals in Simulcast Radio Receivers
Application:
13/172,110 →
Publication:
US 2013/0003637
Delaying Analog Sourced Audio in a Radio Simulcast
Delay Adjustment Using Sample Rate Converters
Circuits and Methods for Providing an Impedance Adjustment
High Breakdown Voltage Integrated Circuit Isolation Structure
Powered Device Including a Multi-Use Detection Resistor
Apparatus Including a Gate Drive Circuit for Selectively Providing Power to a Powered Device Through Multiple Wire Pairs
Sigma-Delta Modulation with Reduction of Spurs Using a Dither Signal
Pll Using Interpolative Divider as Digitally Controlled Oscillator
Performing Power Control in a Receiver Based on Environmental Noise
Techniques to Control Power Consumption in an Iterative Decoder by Control of Node Configurations
Rotating Harmonic Rejection Mixer
Integrated Low-If Terrestrial Audio Broadcast Receiver and Associated Method
Tuner Circuit with an Inter-Chip Transmitter and Method of Providing an Inter-Chip Link Frame
Application:
13/342,619 →
Publication:
US 2012/0099625
Programmable Divider Circuitry for Improved Duty Cycle Consistency and Related Systems and Methods
Patent:
8,406,371 →
Application:
13/343,392 →
Implementing A Passive Rotating Harmonic Rejection Mixer (RHRM) For A TV Tuner In An Integrated Circuit
Multi-Mode Analog-to-Digital Converter
Low Noise Amplifier and Method of Input Impedance Control for Terrestrial and Cable Modes
Providing Voltage Isolation on a Single Semiconductor Die
Capacitive Isolation Receiver Circuitry
Patent:
8,502,584 →
Application:
13/436,146 →
Automatic Gain Control (Agc) for Analog Tv Signals Using Feed-Forward Signal Path Delay
Patent:
8,451,376 →
Application:
13/454,234 →
Digitally Programmable High Voltage Charge Pump
Differential Loopstick Antenna Configuration
Higher-Order Phase Noise Modulator to Reduce Spurs and Quantization Noise
Multiple Signal Format Output Driver with Configurable Internal Load
Sample Rate Estimator for Digital Radio Reception Systems
Controlling Filter Bandwidth Based On Blocking Signals
Successive Approximation Register (SAR) Analog-To-Digital Converter (ADC) Having Optimized Filter
Apparatus for Measuring Noise in an Analog Signal
Patent:
8,593,526 →
Application:
13/586,854 →
Isolation Receiver
Performing Impulse Blanking Based on Blocker Information
Time-Domain Diversity Combining of Signals For Broadcast Receivers
Pop/Click Noise Reduction Circuitry for Power-Up and Power-Down of Audio Output Circuitry
Glitchless Clock Switching That Handles Stopped Clocks
Rotating Harmonic Rejection Mixer
Power Sourcing Equipment and Method of Detecting Inrush Fault Errors
Cascaded Pll for Reducing Low-Frequency Drift in Holdover Mode
Single-Pin Command Technique for Mode Selection and Internal Data Access
Audio Processor Circuits for Acoustic Echo Cancellation and Method Therefor
Television Tuner to Capture a Cable Spectrum
Frequency Synthesizer with Hit-Less Transitions Between Frequency- and Phase-Locked Modes
Patent:
8,786,341 →
Application:
13/833,360 →
Generating Compatible Clocking Signals
Methods And Systems For Rapid Detection Of Digital Radio Signals
Methods And Systems For Blending Between Analog And Digital Broadcast Signals
Air Loop Antenna For Shared AM/FM
Efficient Dual Channel Conversion In A Multi-Band Radio Receiver
Method And Apparatus For Controlling A Harmonic Rejection Mixer
Dac Current Source Matrix Patterns with Gradient Error Cancellation
Rotating Harmonic Rejection Mixer
Antenna Diversity Combining For Differentially Modulated Orthogonal Frequency Division Multiplexed (OFDM) Signals
Method And Apparatus For Controlling A Harmonic Rejection Mixer
Soft Shutdown for Isolated Drivers
Receiver Chip with Multiple Independent Loop-Through Paths
Isolated Serializer-Deserializer
Synchronizing Orthogonal Frequency Division Multiplexed (Ofdm) Symbols in a Receiver
Integrated Circuit with Inter-Chip Link for Boot-Up
Techniques for Reduced Jitter in Digital Isolators
Suppression of Transients in Communications Across an Isolation Barrier
Soft-Start for Isolated Power Converter
Reducing Second Order Distortion in an Amplifier
Managed Timing Engine
Transport of an Analog Signal Across an Isolation Barrier
Updating A Filter Of An Equalizer
Backplane Timing Distribution
Radio Frequency (RF) Receivers Having Whitened Digital Frame Processing And Related Methods
Isolator Including Bi-Directional Regulator
Systems And Methods Using Multiple Inter-Chip (IC) Links For Antenna Diversity And/Or Debug
Patent:
9,178,592 →
Application:
14/340,004 →
Cancellation of Delta-Sigma Quantization Noise Within a Fractional-N Pll with a Nonlinear Time-to-Digital Converter
Cancellation of Spurious Tones Within a Phase-Locked Loop with a Time-to-Digital Converter
Time-To-Voltage Converter Using a Capacitor Based Digital to Analog Converter for Quantization Noise Cancellation
Time-To-Digital Converter Based on a Voltage Controlled Oscillator
Multi-Chip Modules Having Stacked Television Demodulators
Methods And Systems For Rapid Detection Of Digital Content Within RF Signals
Patent:
9,253,007 →
Application:
14/512,739 →
Dual Path Timing Jitter Removal
Solid State Relay Using Capacitive Isolation
Direct-Current to Alternating-Current Power Conversion
Power over Ethernet Powered Device Configured for Low Duty-Cycle Operation
Overvoltage and Surge Protection in a Power Over Ethernet Device
Seamless Linking of Multiple Audio Signals
Noise-Shaping Time-to-Digital Converter
Patent:
9,379,879 →
Application:
14/817,129 →
Horizontal Infrastructure Handling For Integrated Circuit Devices
Circuits and Methods for Providing an Impedance Adjustment
Oscillator Amplifier Biasing Technique to Reduce Frequency Pulling
Patent:
9,602,110 →
Application:
14/963,462 →
Common-Mode Impedance Network for Reducing Sensitivity in Oscillators
Biquad Stage Having a Selectable Bit Precision
Fail Safe Clock Buffer and Clock Generator
Dual Path Timing Wander Removal
Fractional-N Phase-Locked Loop
Removing Impulsive Noise In A Radio
Fully Flexible Multi-Tuner Front End Architecture for a Receiver
Leakage Tolerant Oscillator
Aligning Asynchronous Signals by Time Shifting Information
Patent:
9,673,833 →
Application:
15/196,707 →
Noise Shaping Signed Digital-to-Analog Converter
Patent:
9,705,521 →
Application:
15/221,109 →
Wide Range Glitchless Switchable Clock Divider with Modified 2/3 Divider Stages
Receiver Architecture Having Full-Band Capture And Narrow-Band Paths
Compensating for Thermal Lag in Temperature Compensated Crystal Oscillators
Compensating for Temperature-Dependent Hysteresis in a Temperature Compensated Crystal Oscillator
Isolated Power Transfer Device
Patent:
9,812,989 →
Application:
15/270,470 →
Digital Fast Lock For Phase-Locked Loops
Soft-Start for Isolated Power Converter
Wide Voltage Range Input Interface
Fault Tolerant Communication Channel
Current Limiting for High Current Drivers
Energy Estimation for Thermal Management
Test Interface with Access Across Isolation Barrier
Clamping Inductive Flyback Voltage to Reduce Power Dissipation
Receiver Architecture for Digital Isolators Employing Notch Filters for Common Mode Transient Immunity
Adaptive Signal Compressor for Am Radio
Patent:
10,090,818 →
Application:
15/706,821 →
System, Apparatus And Method For Reducing Audio Artifacts In A Phase Diversity Receiver
Fully Flexible Multi-Tuner Front End Architecture for a Receiver
Power Transfer Device Using an Oscillator
Isolated Power Transfer with Integrated Transformer and Voltage Control
Single Pin Test Interface for Pin Limited Systems
Enhanced Power-Saving Mode in Systems Providing Power Over Transmission Lines
Electromagnetic Radiation Control for Isolated Power Transfer Product
Neutralization of Phase Perturbations from Deterministic Electromagnetic Interference
Isolator with Symmetric Multi-Channel Layout
Low Power Heartbeat for Low Power Mode
Spur Cancellation for Spur Measurement
Time-To-Voltage Converter with Extended Output Range
Time-To-Voltage Converter Using Correlated Double Sampling
System, Apparatus And Method For Time Synchronization Of Delayed Data Streams By Matching Of Wavelet Coefficients
System, Apparatus And Method For Hardware And Software Support Of Radio Functionality
Adaptive Jitter and Spur Adjustment for Clock Circuits
Patent:
10,511,315 →
Application:
16/138,080 →
AC-Coupled Chopper Signal for a High-Impedance Buffer
Power Resonator with Wide Input Voltage Range for Isolated Power Transfer
Spur Canceller with Multiplier-Less Correlator
Spur Cancellation with Adaptive Frequency Tracking
Two Pin Scan Interface for Low Pin Count Devices
High Output Swing High Voltage Tolerant Bus Driver
Patent:
10,461,964 →
Application:
16/169,757 →
Load Compensation to Reduce Deterministic Jitter in Clock Applications
Patent:
10,530,368 →
Application:
16/191,755 →
Relative Frequency Offset Error and Phase Error Detection for Clocks
Patent:
10,608,649 →
Application:
16/194,678 →
Delay Adjustment Using Frequency Estimation
Patent:
10,608,647 →
Application:
16/221,188 →
Failsafe Clock Product Using Frequency Estimation
Patent:
10,483,987 →
Application:
16/221,192 →
Performing Noise Cancellation In Radio Signals Using Spectral Duplication
Patent:
10,419,047 →
Application:
16/225,722 →
Shared Communication Channel That Interleaves 1 PPS Signals and Messaging
Synchronizing Update of Time of Day Counters Using Time Stamp Exchange Over A Control Plane
Maintaining the Correct Time When Counter Values Are Transferred Between Clock Domains
Fractional Divider with Error Correction
Reference Clock Frequency Change Handling in a Phase-Locked Loop
Patent:
10,727,844 →
Application:
16/427,826 →
Using Time-to-Digital Converters to Delay Signals with High Accuracy and Large Range
Locking a Pll to the Nearest Edge of the Input Clock When the Input Clock Is Divided Down Before Use in the Pll
Patent:
10,651,862 →
Application:
16/441,898 →
Use of a Virtual Clock in a PLL to Maintain a Closed Loop System
Patent:
10,727,845 →
Application:
16/451,752 →
Metastable-Free Output Synchronization for Multiple-Chip Systems and the Like
Patent:
10,511,312 →
Application:
16/456,195 →
Interface To Provide Selectable Time Domain Or Frequency Domain Information To Downstream Circuitry
Receiver Intermediate Variable Gain Stage for Isolator Products
Patent:
10,840,861 →
Application:
16/528,059 →
Receiver Front End for Digital Isolators
Demodulator/Detector for Digital Isolators
Patent:
10,840,960 →
Application:
16/528,075 →
Calibration of Digital Isolators
Resistor Based Delta Sigma Multiplying Dac with Integrated Reconstruction Filter
Patent:
10,833,699 →
Application:
16/548,417 →
System, Apparatus And Method For Providing Remote Tuner Options In A Vehicle Entertainment System
Patent:
10,834,356 →
Application:
16/567,386 →
Accurate and Reliable Digital Pll Lock Indicator
Calibration of an Interpolative Divider Using a Virtual Phase-Locked Loop
Patent:
10,833,682 →
Application:
16/582,266 →
Power Transistor Detection with Self-Protection
Spur Cancellation in a Pll System with an Automatically Updated Target Spur Frequency
Patent:
10,819,353 →
Application:
16/593,473 →
Power Transfer Device Using an Oscillator
Load Compensation to Reduce Deterministic Jitter in Clock Applications
Noise Canceling Technique for a Sine to Square Wave Converter
Patent:
10,840,897 →
Application:
16/670,874 →
Gate Driver with Integrated Miller Clamp
On-Chip Phase-Locked Loop Response Measurement
Jitter Self-Test Using Timestamps
Measuring Pin-to-Pin Delays Between Clock Routes
High Dielectric Constant Material at Locations of High Fields
Detection and Management of Frequency Errors in a Reference Input Clock Signal
Patent:
10,908,635 →
Application:
16/726,481 →
Top Hat Structure for Isolation Capacitors
Adjustable Soft Shutdown and Current Booster for Gate Driver
Patent:
10,917,081 →
Application:
16/815,435 →
Flexible Fault Detection
Secondary Phase Compensation Assist for Pll Io Delay
Patent:
11,088,819 →
Application:
16/836,706 →
Secondary Phase Compensation Assist for Pll Io Delay Aligning Sync Signal to System Clock Signal
Patent:
11,088,816 →
Application:
16/836,713 →
Calibration of the External Resistance Value in the Power Sourcing Equipment of a Poe System
Phase Transport with Frequency Translation Without a Pll
Instrument Noise Correction for Jitter Measurements
Measurement and Calibration of Mismatch in an Isolation Channel
Peak and Gain Calibration of a Receiver in an Isolation Product
Demodulator for an Isolation Communication Channel for Dual Communication
Transmitter for Dual Communication Over an Isolation Channel
Interface for Passing Control Information Over an Isolation Channel
System, Apparatus And Method For Providing Remote Tuner Options In A Vehicle Entertainment System
Measurement Circuit for Isolation Product
Supply-Glitch-Tolerant Regulator
High-Speed Low-Impedance Boosting Low-Dropout Regulator
System and Method for Blind Channel Estimation and Coherent Differential Equalization in an Orthogonal Frequency Division Multiplexing (Ofdm) Receiver
Deglitcher Circuit with Integrated Non-Overlap Function
Patent:
11,258,432 →
Application:
17/125,561 →
Fsync Mismatch Tracking
Variable Current Drive for Isolated Gate Drivers
Validation of Current Levels Delivered by a Gate Driver
Calibration of a Time-to-Digital Converter Using a Virtual Phase-Locked Loop
Patent:
11,283,459 →
Application:
17/217,695 →
Updating Control Parameters of a Gate Driver During Operation
Calibration of Driver Output Current
Gate Driver Output Protection Circuit
Frequency Modulation Tracking for Band Rejection to Reduce Dynamic Range
Patent:
11,258,643 →
Application:
17/323,782 →
Signal Delay Control Using a Recirculating Delay Loop and a Phase Interpolator
Isolation Communications Channel Using Direct Demodulation and Data-Edge Encoding
Phase Noise Performance Using Multiple Resonators with Varying Quality Factors and Frequencies
Application:
17/354,089 →
Publication:
US 2022/0407526
Data Protocol Over Clock Line
Patent:
11,502,812 →
Application:
17/375,634 →
Auto-detection of an externally provided reference clock frequency
Application:
60/217,207 →
Digitally-synthesized loop filter capacitor
Application:
60/217,208 →
Clock and data recovery circuit without jitter peaking
Application:
60/278,784 →
Use of dual hysteresis modes in determining a loss of signal output indication
Application:
60/302,902 →
Auto-detection between referenceless and reference clock mode of operation
Application:
60/302,932 →
Offset correction and slicing level adjustment for amplifier circuits
Application:
60/302,935 →
Method and apparatus for adjusting the phase of an output of a phase-locked loop
Application:
60/360,497 →
Method and apparatus for generating a clock signal in holdover mode
Application:
60/462,266 →
Multi-functional output enable terminal
Application:
60/467,813 →
Communication devices capable of using system clock inputs for embedded television applications
Application:
60/560,042 →
Method and apparatus for a programmable clock source generating a wide range of output frequencies
Application:
60/567,479 →
Method and apparatus for noise compensation in an oscillator circuit
Application:
60/582,972 →
Integrated PLL loop filter and charge pump
Application:
60/640,476 →
Cancellation of undesired portions of audio signals
Application:
60/695,335 →
Expanded pull range for a voltage controlled clock synthesizer
Application:
60/763,503 →
Direct Digital Interpolative Synthesis
Application:
60/827,325 →
Hitless Switching Architecture
Application:
60/827,530 →
Isolator Circuit Including a Voltage Regulator
Application:
60/946,064 →
Stereo noise mitigation techniques
Application:
61/065,605 →
Frequency Adjustment for Clock Generator
Application:
61/090,369 →
Buffer with an Output Swing Created Using an Over-Supply Voltage
Application:
61/166,076 →
FM Receiver Multipath Noise Mitigation Scheme
Application:
61/235,195 →
Multi-Mode Analog-to-Digital Converter
Application:
61/556,263 →
Controlling Filter Bandwidth Based On Blocking Signals
Application:
61/617,123 →
Apparatus for Measuring Noise in an Analog Signal
Application:
61/663,491 →
Managed Timing Engine
Application:
61/803,666 →
Isolated Serializer-Deserializer
Application:
61/812,528 →
Backplane Timing Distribution
Application:
61/826,138 →
Transport of an Analog Signal Across an Isolation Barrier
Application:
61/872,537 →
Multi-Chip Modules Having Stacked Television Demodulators
Application:
61/880,263 →
Fractional-N Pll
Application:
61/909,490 →
Suppression of Transients in Communications Across an Isolation Barrier
Application:
61/918,416 →
Distribution of Time-of-Day (Tod) and 1 Pulse-Per-Second (1 Pps) to Line Cards in Ieee 1588 Central Timing Architecture
Application:
62/683,464 →
Variable-Current Drive for Isolated Gate Drivers
Application:
63/121,702 →
Efficiently Updating Control Parameters of Gate Drivers During Operation
Application:
63/121,949 →
Enumeration of Peripheral Devices on a Serial Communication Bus
Application:
63/124,381 →
On-Chip Generation of Positive and Negative Switch Gate Control Voltages for Gate Driver Applications
Application:
63/125,226 →
Management of Multiple Switching-Synchronized Measurements Using Combined Prioritized Measurement and Round-Robin Sequence Measurement
Application:
63/126,050 →
Related Assignments
(10)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Sep 7, 2001
From: STEINER, PHILIP DAVID; PEPENELLA, GERARD
To: SILICON LABORATORIES, INC.
Reel/Frame 012158/0921 →
Assignment of Assignor's Interest
Sep 17, 2001
From: PERROTT, MICHAEL H.
To: SILICON LABORATORIES, INC.
Reel/Frame 012164/0410 →
Assignment of Assignor's Interest
Sep 21, 2001
From: PERROTT, MICHAEL H.
To: SILICON LABORATORIES, INC.
Reel/Frame 012193/0819 →
Assignment of Assignor's Interest
Dec 27, 2001
From: PERROTT, MICHAEL H.; BAIRD, REX T.; HUANG, YUNTENG
To: SILICON LABORATORIES, INC.
Reel/Frame 012395/0308 →
Assignment of Assignor's Interest
Dec 27, 2001
From: PERROTT, MICHAEL H.; HEIN, JERRELL P.; BAIRD, REX T.
To: SILICON LABORATORIES, INC.
Reel/Frame 012395/0276 →
Assignment of Assignor's Interest
Dec 31, 2001
From: KING, ERIC T.; PERROTT, MICHAEL H.; PASTORELLO, DOUGLAS F.
To: SILICON LABORATORIES, INC.
Reel/Frame 012442/0949 →
Assignment of Assignor's Interest
Jan 14, 2002
From: GOLDENBERG, MARIUS
To: SILICON LABORATORIES, INC.
Reel/Frame 012467/0349 →
Assignment of Assignor's Interest
Nov 10, 2003
From: PCTEL, INC.
To: SILICON LABORATORIES INC.
Reel/Frame 014675/0579 →
Assignment of Assignor's Interest
Nov 24, 2003
From: CONEXANT SYSTEMS, INC.
To: PCTEL, INC.
Reel/Frame 014734/0539 →
Assignment of Assignor's Interest
Apr 28, 2016
From: SRINIVAS, SHAIL
To: SILICON LABORATORIES INC.
Reel/Frame 038403/0246 →