Method and apparatus for controlling a harmonic rejection mixer
View Patent ↗In one embodiment, the present invention includes a method for receiving a radio frequency (RF) signal and mixing the RF signal with a master clock to obtain a mixed signal, cyclically rotating the mixed signal to each of N gain stages for at least one cycle of the master clock, and summing the outputs of the N gain stages to provide an output signal.
1. A method comprising:
receiving an incoming radio frequency (RF) signal and mixing the incoming RF signal with a master clock, the master clock corresponding to a multiplied version of a local oscillator (LO) frequency, to obtain a mixed signal;
cyclically rotating the mixed signal to each of a plurality of N gain stages for at least one cycle of the master clock during a cycle of the LO; and
summing the outputs of the plurality of N gain stages to provide an output signal.
2. The method of claim 1 , further comprising cyclically rotating the mixed signal from a first one to a second one of the plurality of N gain stages when the master clock is at a low value.
3. The method of claim 1 , wherein the plurality of N gain stages each comprises an impedance corresponding to a weighted value obtained from a unitary impedance value and a predetermined weighted value.
4. The method of claim 3 , wherein the plurality of N gain stages further comprises a unity gain buffer having an output coupled to the impedance.
5. The method of claim 1 , further comprising cyclically rotating the mixed signal such that each of the plurality of N gain stages is to receive the mixed signal for a predetermined portion of the LO cycle.
6. The method of claim 5 , further comprising cyclically rotating the mixed signal to less than all of the plurality of N gain stages, based at least in part on a frequency of the incoming RF signal.
7. The method of claim 6 , further comprising reducing or preventing harmonic rejection by matching passive components in the plurality of N gain stages, wherein an RF mixer that mixes the incoming RF signal includes a single differential transconductor.
8. The method of claim 1 , further comprising cyclically rotating positive and negative portions of the mixed signal in a complementary fashion to each of first and second sets of the plurality of N gain stages.
9. The method of claim 8 , wherein each of the plurality of N gain stages includes a gain buffer having an output coupled to an impedance having a first weighted value or a second weighted value.
10. The method of claim 9 , wherein the first weighted value corresponds to a ratio of a unitary impedance value and a predetermined value, wherein the predetermined value equals
sin
(
2
π
N
k
)
,
where k is 0 to N−1, and the second weighted value corresponds to a ratio of the unitary impedance value and a second predetermined value, wherein the second predetermined value equals
cos
(
2
π
N
k
)
.
11. An apparatus comprising:
a low noise amplifier (LNA) to receive an incoming radio frequency (RF) signal;
a mixer to mix the incoming RF signal with a master clock to obtain a mixed signal, the master clock corresponding to a multiplied version of a local oscillator (LO) frequency;
a plurality of N gain stages each to receive a cyclical rotation of the mixed signal for at least one cycle of the master clock during a cycle of the LO; and
a summer to sum the outputs of the plurality of N gain stages to provide an output signal.
12. The apparatus of claim 11 , further comprising a switch to cyclically rotate the mixed signal from a first one to a second one of the plurality of N gain stages when the master clock is at a low value.
13. The apparatus of claim 11 , wherein the plurality of N gain stages each comprises an impedance corresponding to a weighted value obtained from a unitary impedance value and a predetermined weighted value.
14. A method comprising:
receiving an incoming radio frequency (RF) signal in a single differential transconductor of a mixer and mixing the incoming RF signal with a master clock in master local oscillator (LO) devices of the mixer, the master clock corresponding to a multiplied version of a LO frequency, to obtain a mixed signal;
cyclically rotating the mixed signal to each of a plurality of N gain stages via N rotational switches for at least one cycle of the master clock during a cycle of the LO; and
summing the outputs of the plurality of N gain stages to provide an output signal.
15. The method of claim 14 , further comprising cyclically rotating the mixed signal from a first one to a second one of the plurality of N gain stages when the master clock is at a low value.
16. The method of claim 14 , wherein the plurality of N gain stages each comprises an impedance corresponding to a weighted value obtained from a unitary impedance value and a predetermined weighted value.
17. The method of claim 16 , wherein the plurality of N gain stages further comprises a unity gain buffer having an output coupled to the impedance.
18. The method of claim 14 , further comprising cyclically rotating the mixed signal such that each of the plurality of N gain stages is to receive the mixed signal for a predetermined portion of the LO cycle.
19. The method of claim 18 , further comprising cyclically rotating the mixed signal to less than all of the plurality of N gain stages, based at least in part on a frequency of the incoming RF signal.