Noise-shaping time-to-digital converter

1. An apparatus comprising:

a time-to-digital converter comprising:

a phase detector configured to generate a phase error signal based on a phase-adjusted feedback signal and an input signal;

a loop filter configured to integrate the phase error signal and generate an analog integrated phase error signal; and

an analog-to-digital converter configured to convert the analog integrated phase error signal to a digital phase error code;

a digital-to-time converter configured to convert at least a portion of the digital phase error code to a gating signal based on a reference clock signal and an enable signal; and

a feedback circuit configured to generate the phase-adjusted feedback signal based on the reference clock signal and the gating signal.

2. The apparatus, as recited in claim 1 , wherein the digital-to-time converter selectively provides as the gating signal, a version of the enable signal selected from a plurality of versions of the enable signal according to the digital phase error code.

3. The apparatus, as recited in claim 2 , wherein the feedback circuit gates the reference clock signal with the gating signal to generate the phase-adjusted feedback signal.

4. The apparatus, as recited in claim 1 , wherein the digital-to-time converter converts a most-significant portion of the digital phase error code to the gating signal and the feedback circuit comprises:

a second digital-to-time converter configured to convert a least significant portion of the digital phase error code to the phase-adjusted feedback signal based on the gating signal.

5. The apparatus, as recited in claim 1 , wherein the time-to-digital converter is configured as an error generation circuit responsive to the enable signal received from a coarse time-to-digital converter, the digital phase error code corresponding to a quantization error of a second digital phase error code, the apparatus further comprising:

a coarse time-to-digital converter configured to generate the second digital phase error code; and

an output circuit configured to combine the digital phase error code and the second digital phase error code to generate a digital output signal indicative of an input time interval.

6. The apparatus, as recited in claim 1 , further comprising:

a digital loop filter configured to integrate the digital phase error code to generate a digital integrated phase error code;

a digitally controlled oscillator configured to generate an output clock signal based on the digital integrated phase error code;

a digital-to-frequency converter configured to generate the enable signal based on a digital frequency code and the output clock signal.

7. The apparatus, as recited in claim 1 , wherein the time-to-digital converter shapes noise in the phase domain and maintains at least first-order noise shaping in the phase-adjusted feedback signal.

8. The apparatus, as recited in claim 1 , wherein generation of the phase-adjusted feedback signal based on the reference clock signal has linear gain.

9. A method comprising:

converting an input signal to a digital phase error code comprising:

generating a phase error signal based on a phase-adjusted feedback signal and the input signal;

integrating the phase error signal to generate an analog integrated phase error signal;

converting the analog integrated phase error signal to the digital phase error code;

converting at least a portion of the digital phase error code to a gating signal based on a reference clock signal and an enable signal; and

generating the phase-adjusted feedback signal based on the reference clock signal and the gating signal.

10. The method, as recited in claim 9 , wherein converting at least a portion of the digital phase error code to the gating signal comprises selecting a version of the enable signal from a plurality of versions of the enable signal according to the digital phase error code.

11. The method, as recited in claim 9 , wherein generating the phase-adjusted feedback signal comprises gating the reference clock signal with the gating signal to generate the phase-adjusted feedback signal.

12. The method, as recited in claim 9 , wherein only the most-significant portion of the digital phase error code is converted to the gating signal and generating the phase-adjusted feedback signal comprises:

converting a least significant portion of the digital phase error code to the phase-adjusted feedback signal based on the gating signal.

13. The method, as recited in claim 9 , further comprising:

generating a second digital phase error code; and

combining the digital phase error code and the second digital phase error code to generate a digital output signal indicative of an input time interval, wherein the enable signal is a delayed version of the input signal.

14. The method, as recited in claim 9 , further comprising:

integrating the digital phase error code to generate a digital integrated phase error code;

generating an output clock signal based on the digital integrated phase error code;

generating the enable signal based on a digital frequency code and the output clock signal.

15. The method, as recited in claim 9 , wherein the converting the input signal to the digital phase error shapes noise in the phase domain and maintains at least first-order noise shaping in the phase-adjusted feedback signal.

16. The method, as recited in claim 9 , wherein generation of the phase-adjusted feedback signal based on the reference clock signal has linear gain.

17. The method, as recited in claim 9 , further comprising:

integrating the digital phase error code to generate a digital integrated phase error code;

generating a frequency error code based on the digital integrated phase error code and a target frequency code;

integrating the frequency error code to generate a digital control code;

generating an output clock signal based on the digital control code, the output clock signal being provided as the reference clock signal.