Neutralization of phase perturbations from deterministic electromagnetic interference

1. A clock generator comprising:

an oscillator configured to generate an oscillating signal; and

a signal path coupled to the oscillator and configured to provide an output clock signal based on the oscillating signal, the signal path comprising a frequency divider configured to generate the output clock signal having an output frequency, a ratio of the output frequency and a first frequency of the oscillating signal being a fractional number,

wherein in response to a control signal, the signal path is configured to neutralize periodic phase perturbations in the oscillating signal using opposing periodic phase perturbations.

2. The clock generator, as recited in claim 1 , wherein the signal path is responsive to the control signal to adjust a duty cycle, a rise time, or a fall time of the output clock signal to cause alternating phase perturbations of the periodic phase perturbations to apply as the opposing periodic phase perturbations in the output clock signal.

3. The clock generator, as recited in claim 1 , wherein the control signal is configured to adjust a duty cycle of the output clock signal to cause an integer number of periods of the oscillating signal to occur between a rising edge of the output clock signal and a next falling edge of the output clock signal.

4. The clock generator, as recited in claim 1 , wherein the frequency divider comprises:

an interpolative divider responsive to a fractional divider value, a fractional duty cycle adjustment value, and an indication of a polarity of the output clock signal, the interpolative divider being configured to implement a duty cycle adjustment based on the fractional duty cycle adjustment value with a zero net frequency change from a frequency indicated by the fractional divider value.

5. The clock generator, as recited in claim 4 , wherein the fractional duty cycle adjustment value configures the interpolative divider to adjust rising edges of the output clock signal and falling edges of the output clock signal to coincide with equal locations of an impulse sensitivity function of the oscillating signal.

6. The clock generator, as recited in claim 4 , wherein the signal path further comprises:

a pull-up circuit responsive to a rise time control signal; and

a pull-down circuit responsive to a fall time control signal,

wherein the pull-up circuit and the pull-down circuit are configured to cause a rise time of the output clock signal and a fall time of the output clock signal to provide a predetermined amount of neutralization.

7. The clock generator, as recited in claim 1 , wherein the periodic phase perturbations are injected into the oscillating signal by deterministic electromagnetic interference.

8. The clock generator, as recited in claim 1 , wherein the oscillator is a free-running oscillator.

9. The clock generator, as recited in claim 1 , further comprising:

an additional signal path configured to generate an additional output clock signal in response to the oscillating signal,

the additional signal path being responsive to an additional control signal to adjust a duty cycle, a rise time, or a fall time of the additional output clock signal to cause alternating phase perturbations of the periodic phase perturbations to apply opposing phase perturbations to the additional output clock signal.

10. A clock generator comprising:

an oscillator configured to generate an oscillating signal, the oscillator comprising a tank circuit configured to oscillate at a nominal frequency;

a signal path configured to provide an output clock signal based on the oscillating signal;

an auxiliary path configured to provide an auxiliary signal to the oscillator, the auxiliary signal being based on the oscillating signal and configured according to a control signal to generate a signal having a magnitude equal to a second magnitude of an induced signal in the oscillator and a polarity opposite to a second polarity of the induced signal, the auxiliary path comprising a selectable capacitance circuit or a selectable inductor circuit responsive to the control signal to provide the auxiliary signal to the tank circuit,

wherein in response to the control signal, the clock generator is configured to neutralize periodic phase perturbations in the oscillating signal using opposing periodic phase perturbations,

wherein the clock generator is configured to use the opposing periodic phase perturbations in the oscillator.

11. The clock generator, as recited in claim 10 , wherein the auxiliary path comprises

the selectable capacitance circuit responsive to the control signal to provide the auxiliary signal to the tank circuit.

12. A method for reducing jitter in an output clock signal of a clock generator, the method comprising:

generating an oscillating signal; and

providing the output clock signal in response to generation of the oscillating signal,

wherein providing the output clock signal comprises:

generating the output clock signal having an output frequency that is a first frequency of the oscillating signal divided by a fractional number; and

in response to a control signal, neutralizing periodic phase perturbations in the oscillating signal using opposing periodic phase perturbations, the neutralizing comprising adjusting a duty cycle of the output clock signal to cause an integer number of periods of the oscillating signal to occur between a rising edge of the output clock signal and a next falling edge of the output clock signal.

13. The method, as recited in claim 12 , wherein the neutralizing:

causes alternating phase perturbations of the periodic phase perturbations to apply opposing phase perturbations to the output clock signal.

14. The method, as recited in claim 13 , wherein the neutralizing further comprises:

adjusting a rise time of the output clock signal or a fall time of the output clock signal to cause the rise time and the fall time to provide a predetermined amount of neutralization.

15. The method, as recited in claim 12 , wherein the neutralizing:

causes rising edges of the output clock signal and falling edges of the output clock signal to coincide with equal locations of an impulse sensitivity function of the oscillating signal.

16. The method, as recited in claim 12 ,

wherein the neutralizing implements the duty cycle of the output clock signal based on a fractional duty-cycle adjustment value with a zero net frequency change from a frequency indicated by a fractional divider value provided to generate the output clock signal.