High breakdown voltage integrated circuit isolation structure
View Patent ↗A high breakdown voltage integrated circuit isolator device communicates a digital signal from a signal input on one semiconductor die to a signal output on another semiconductor die while providing high voltage isolation between the signal input and the signal output. Each die may include a respective capacitive isolation barrier structure that couple together via a bonding wire between combined top metal/bonding pads of the capacitive isolation barrier structures.
1. An integrated circuit isolator device, comprising:
a first die including:
first circuitry, and
a first isolation barrier structure, coupled to the first circuitry, the first isolation barrier structure including a combined top plate/bonding pad and a bottom plate and insulative material therebetween, the bottom plate of the first isolation barrier structure being coupled to the first circuitry;
a first circuitry keep-out region, situated on the first die proximate the first circuitry, wherein a metal layer of the first circuitry does not extend into the first circuitry keep-out region;
a second die including:
second circuitry, and
a second isolation barrier structure, coupled to the second circuitry, the second isolation barrier structure including a combined top plate/bonding pad and a bottom plate and insulative material therebetween, the bottom plate of the second isolation barrier structure being coupled to the second circuitry;
a bond wire coupling the combined top plate/bonding pad of the first isolation barrier structure to the combined top plate/bonding pad of the second isolation barrier structure, such that a signal propagates from the first circuitry, through the first and second isolation barrier structures, and to the second circuitry in voltage-isolated fashion.
2. The integrated circuit isolator device of claim 1 , wherein the first isolation barrier structure is a capacitive isolation structure and the second isolation barrier structure is a capacitive isolation structure.
3. An integrated circuit isolator device, comprising:
a first die including:
transmitter circuitry, and
a first capacitive isolation structure, coupled to the transmitter circuitry, the first capacitive isolation structure including a combined top plate/bonding pad and a bottom plate and insulative material therebetween, the bottom plate of the first capacitive isolation structure being coupled to the transmitter circuitry;
a first circuitry keep-out region, situated on the first die and surrounding the combined top plate/bonding pad of the first capacitive isolation structure, the first circuitry being configured such that a metal layer of the first circuitry does not extend into the first circuitry keep-out region;
a second die including:
receiver circuitry, and
a second capacitive isolation structure, coupled to the receiver circuitry, the second capacitive isolation structure including a combined top plate/bonding pad and a bottom plate and insulative material therebetween, the bottom plate of the second capacitive isolation structure being coupled to the receiver circuitry;
a bond wire coupling the combined top plate/bonding pad of the first capacitive isolation structure to the combined top plate/bonding pad of the second capacitive isolation structure, such that a signal propagates from the transmitter circuitry, through the first and second capacitive isolation structures, and to the receiver circuitry in voltage-isolated fashion.
4. The integrated circuit isolator device of claim 3 , further comprising a plurality of circuitry keep-out regions situated on the first die and surrounding the combined top plate/bonding pad of the first capacitive isolation structure, the circuitry keep-out regions of the plurality of circuitry keep-out regions corresponding to respective metal layers of the transmitter circuitry.
5. The integrated circuit isolator device of claim 4 , wherein each circuitry keep-out region exhibits respective dimensions, the dimensions of the circuitry keep-out regions increasing in size from a bottom of the first capacitive isolation structure to a top of the first capacitive isolation structure.
6. The integrated circuit isolator device of claim 3 , further comprising:
a first insulative material situated on a top surface of the first die except for a first insulative material keep-out region that surrounds the combined top plate/bonding pad of the first capacitive isolation structure.
7. A method of fabricating an integrated circuit isolator device, the method comprising:
fabricating in a first die: transmitter circuitry, and a first capacitive isolation structure, coupled to the transmitter circuitry, the first capacitive isolation structure including a combined top plate/bonding pad and a bottom plate and insulative material therebetween, the bottom plate of the first capacitive isolation structure being coupled to the transmitter circuitry;
fabricating a first circuitry keep-out region, situated on the first die and surrounding the combined top plate/bonding pad of the first capacitive isolation structure, the first circuitry being configured such that a metal layer of the first circuitry does not extend into the first circuitry keep-out region;
fabricating in a second die: receiver circuitry, and a second capacitive isolation structure, coupled to the receiver circuitry, the second capacitive isolation structure including a combined top plate/bonding pad and a bottom plate and insulative material therebetween, the bottom plate of the second capacitive isolation structure being coupled to the receiver circuitry;
coupling with a bond wire the combined top plate/bonding pad of the first capacitive isolation structure to the combined top plate/bonding pad of the second capacitive isolation structure, such that a signal propagates from the transmitter circuitry, through the first and second capacitive isolation structures, and to the receiver circuitry in voltage-isolated fashion.
8. The method of claim 7 , further comprising fabricating a plurality of circuitry keep-out regions situated on the first die and surrounding the combined top plate/bonding pad of the first capacitive isolation structure, the circuitry keep-out regions of the plurality of circuitry keep-out regions corresponding to respective metal layers of the transmitter circuitry.
9. The method of claim 8 , wherein each circuitry keep-out region exhibits respective dimensions, the dimensions of the circuitry keep-out regions increasing in size from a bottom of the first capacitive isolation structure to a top of the first capacitive isolation structure.
10. The method of claim 7 , further comprising fabricating a first insulative material situated on a top surface of the first die except for a first insulative material keep-out region that surrounds the combined top plate/bonding pad of the first capacitive isolation structure.