Sigma-delta modulation with reduction of spurs using a dither signal

1. A method comprising:

sigma-delta modulating a combination of a dither signal and an input signal to generate a first signal;

sigma-delta modulating a signal based on the dither signal to generate a second signal; and

generating a first control signal based on a difference between the first signal and the second signal.

2. The method as recited in claim 1 ,

wherein sigma-delta modulating the combination generates a third signal,

wherein sigma-delta modulating the signal based on the dither signal generates a fourth signal, and

wherein the method further comprises generating a second control signal based on a difference between the third signal and the fourth signal.

3. The method as recited in claim 2 ,

wherein the input signal corresponds to a digital frequency ratio,

wherein the first control signal corresponds to an integer portion of the digital frequency ratio, the first signal comprising a stream of integers that approximate the digital frequency ratio, and

wherein the second control signal corresponds to a digital quantization error corresponding to a fractional portion of the digital frequency ratio.

4. The method as recited in claim 3 , further comprising:

generating a first clock signal having a first frequency; and

dividing the first clock signal according to the first control signal to generate a second clock signal having a second frequency.

5. The method as recited in claim 4 , further comprising:

generating a third clock signal by adjusting a phase of the second clock signal based on the fractional portion.

6. The method as recited in claim 5 ,

wherein a phase noise characteristic associated with the third clock signal does not include digitally-caused spurs,

wherein the third clock signal has a jitter characteristic of no more than two least-significant bits of peak-to-peak jitter, and

wherein the phase noise characteristic is substantially flat.

7. The method as recited in claim 1 ,

wherein an amplitude of the dither signal is at least half an amplitude of the input signal.

8. The method as recited in claim 7 ,

wherein the amplitude of the dither signal is approximately equal to the amplitude of the input signal.

9. The method as recited in claim 1 ,

wherein the signal based on the dither signal is further based on the input signal.

10. An apparatus comprising:

a first sigma-delta modulator coupled to generate a first signal in response to a dither signal and an input signal;

a second sigma-delta modulator coupled to generate a second signal in response to the dither signal; and

a first circuit coupled to generate a first control signal based on a difference between the first signal and the second signal.

11. The apparatus as recited in claim 10 ,

wherein the first sigma-delta modulator is further coupled to generate a third signal in response to the dither signal and the input signal,

wherein the second sigma-delta modulator is further coupled to generate a fourth signal in response to the dither signal,

and further comprising a second circuit coupled to generate a second control signal indicating a difference between the third signal and the fourth signal.

12. The apparatus as recited in claim 11 ,

wherein the first sigma-delta modulator includes multiple quantizers coupled to generate the first signal and the third signal, and

wherein the second sigma-delta modulator includes multiple quantizers coupled to generate the second signal and the fourth signal.

13. The apparatus as recited in claim 11 , further comprising:

an interpolative divider that includes:

a fractional divider responsive to the first control signal; and

a phase interpolator responsive to the second control signal.

14. The apparatus as recited in claim 13 ,

wherein the fractional divider is further responsive to a first clock signal, the fractional divider coupled to generate a second clock signal based on the first control signal and based on the first clock signal, and

wherein the phase interpolator is coupled to generate a third clock signal by interpolating phases of the second clock signal based on the second control signal.

15. The apparatus as recited in claim 13 ,

wherein the interpolative divider is included in a frequency synthesizer having an open-loop configuration.

16. The apparatus as recited in claim 11 ,

wherein the first sigma-delta modulator and the second sigma-delta modulator are first-order sigma-delta modulators.

17. The apparatus as recited in claim 10 ,

wherein an amplitude of the dither signal is approximately equal to an amplitude of the input signal.

18. A method comprising:

operating on a sigma-delta modulated signal to reduce a dither signal component in one of a first signal and a second signal, the first signal being an integer portion corresponding to a digital frequency ratio and the second signal corresponding to a fractional portion of the digital frequency ratio.

19. The method as recited in claim 18 , further comprising:

sigma-delta modulating a combination of an input signal and a dither signal corresponding to the dither signal component to generate the sigma-delta modulated signal,

wherein an amplitude of the dither signal is approximately equal to an amplitude of the input signal.

20. The method as recited in claim 18 ,

wherein the operation is performed digitally in a frequency synthesizer.