Method and apparatus for controlling a harmonic rejection mixer
View Patent ↗In one embodiment, the present invention includes a method for receiving a radio frequency (RF) signal and mixing the RF signal with a master clock to obtain a mixed signal, cyclically rotating the mixed signal to each of N gain stages for at least one cycle of the master clock, and summing the outputs of the N gain stages to provide an output signal.
1. A system comprising:
a low noise amplifier (LNA) to receive a radio frequency (RF) signal;
a voltage controlled oscillator (VCO) to generate a VCO frequency;
a frequency divider to divide the VCO frequency to obtain a master clock signal corresponding to a local oscillator (LO) multiplied by N;
a mixer coupled to an output of the LNA, the mixer to mix the RF signal with the master clock signal to obtain a mixed signal;
a switch coupled to an output of the mixer to switch the mixed signal to a plurality of gain stages; and
the plurality of gain stages to each receive the mixed signal from the switch for a portion of a cycle of the LO, wherein N corresponds to an active number of the plurality of gain stages.
2. The system of claim 1 , wherein the mixer comprises:
a differential transconductor gated by the RF signal and to pass an RF current; and
a mix stage to receive the RF current, the mix stage gated by the master clock signal and to pass a mixed current.
3. The system of claim 2 , wherein the switch comprises a plurality of rotating switches each having a transistor to receive the mixed current and to output the mixed signal when the transistor is enabled by a control signal, wherein a value of the control signal is changed when a value of the master clock signal is at a low state.
4. The system of claim 3 , further comprising a plurality of mixer loads coupled between the plurality of rotating switches and the plurality of gain stages, wherein the plurality of gain stages are split into an in-phase portion and a quadrature portion.
5. The system of claim 4 , wherein the in-phase portion of the plurality of gain stages each comprises an impedance having a value that equals a ratio of a unitary impedance value and a predetermined value that equals
sin
(
2
π
N
k
)
,
where k is 0 to N−1, and a unity gain buffer having an output coupled to the impedance.
6. The system of claim 5 , wherein the quadrature portion of the plurality of gain stages each comprises an impedance having a second value that equals a ratio of the unitary impedance value and a second predetermined value that equals
cos
(
2
π
N
k
)
,
where k is 0 to N−1, and the unity gain buffer having an output coupled to the impedance.
7. The system of claim 6 , further comprising:
a summer to combine outputs of the plurality of gain stages;
a low pass filter (LPF) coupled to an output of the summer;
an analog-to-digital converter (ADC) coupled to an output of the LPF; and
a demodulator coupled to an output of the ADC.
8. A method comprising:
receiving a request for a channel at a first frequency;
determining a number of stages N to be enabled in a mixer of a system including a low noise amplifier (LNA) to receive a radio frequency (RF) signal, a voltage controlled oscillator (VCO) to generate a VCO frequency, a frequency divider to divide the VCO frequency to obtain a master clock signal corresponding to a local oscillator (LO) multiplied by N, the mixer coupled to an output of the LNA to mix the RF signal with the master clock signal to obtain a mixed signal, a switch coupled to an output of the mixer to switch the mixed signal to a plurality of gain stages each to receive the mixed signal from the switch for a portion of a cycle of the LO, wherein N corresponds to an active number of the plurality of gain stages, based at least in part on the first frequency;
selecting the master clock frequency and providing the master clock frequency to the mixer; and
mixing the RF signal that includes the channel with the master clock frequency and providing the mixed signal to each of N of the plurality of gain stages individually for a portion of each LO cycle.
9. The method of claim 8 , further comprising summing an output of each of the N stages for each LO cycle.
10. The method of claim 8 , further comprising determining N to be less than all available gain stages if the channel is in a band less than a predetermined frequency.
11. The method of claim 8 , further comprising receiving a request for the channel at the first frequency.
12. The method of claim 11 , further comprising:
receiving a second request for a second channel at a second frequency; and
dynamically updating a number of gain stages N to be enabled based on the second frequency.
13. The method of claim 12 , further comprising determining the number of gain stages N based at least in part on a power consumption level for a receiver.
14. The method of claim 13 , further comprising determining the number of gain stages N based at least in part on a harmonic rejection level for the receiver.
15. A system comprising:
a low noise amplifier (LNA) to receive a radio frequency (RF) signal;
a controlled oscillator to generate a first frequency;
a frequency divider to divide the first frequency to obtain a master clock signal corresponding to a local oscillator (LO) multiplied by N;
a rotating mixer coupled to an output of the LNA, the rotating mixer to mix the RF signal with the master clock signal to obtain a mixed signal;
a switch coupled to an output of the mixer to switch the mixed signal to a plurality of gain stages; and
the plurality of gain stages to each receive the mixed signal from the switch for a portion of a cycle of the LO, wherein N corresponds to an active number of the plurality of gain stages.
16. The system of claim 15 , wherein each of the plurality of gain stages has a different gain factor associated therewith.
17. The system of claim 15 , wherein the rotating mixer comprises:
a differential transconductor gated by the RF signal and to pass an RF current; and
a mix stage to receive the RF current, the mix stage gated by the master clock signal and to pass a mixed current.
18. The system of claim 17 , wherein the switch comprises a plurality of rotating switches each having a transistor to receive the mixed current and to output the mixed signal when the transistor is enabled by a control signal, wherein a value of the control signal is changed when a value of the master clock signal is at a low state.
19. The system of claim 18 , further comprising a plurality of mixer loads coupled between the plurality of rotating switches and the plurality of gain stages, wherein the plurality of gain stages are split into an in-phase portion and a quadrature portion.
20. The system of claim 19 , wherein the in-phase portion of the plurality of gain stages each comprises an impedance having a value that equals a ratio of a unitary impedance value and a predetermined value that equals
sin
(
2
π
N
k
)
,
where k is 0 to N−1, and a unity gain buffer having an output coupled to the impedance.
21. The system of claim 20 , wherein the quadrature portion of the plurality of gain stages each comprises an impedance having a second value that equals a ratio of the unitary impedance value and a second predetermined value that equals
cos
(
2
π
N
k
)
,
where k is 0 to N−1, and the unity gain buffer having an output coupled to the impedance.
22. The system of claim 15 , further comprising:
a summer to combine outputs of the plurality of gain stages;
a low pass filter (LPF) coupled to an output of the summer;
an analog-to-digital converter (ADC) coupled to an output of the LPF; and
a demodulator coupled to an output of the ADC.
23. The system of claim 15 , wherein the rotating mixer comprises a rotating harmonic rejection mixer.
24. The system of claim 15 , wherein the plurality of gain stages operate at an intermediate frequency (IF).