Reference clock frequency change handling in a phase-locked loop
A method for operating a phase-locked loop includes generating a phase difference signal based on an input clock signal and a feedback clock signal. The method includes filtering a loop filter input signal based on the phase difference signal to generate a loop filter output signal. The feedback clock signal is based on the loop filter output signal. The method includes transitioning a frequency of an output clock signal of the phase-locked loop from a first frequency to a target frequency responsive to detection of a catastrophic cycle slip event in the absence of an out-of-frequency event.
1. A method for operating a phase-locked loop comprising:
generating a phase difference signal based on an input clock signal and a feedback clock signal;
filtering a loop filter input signal based on the phase difference signal to generate a loop filter output signal, the feedback clock signal being based on the loop filter output signal; and
transitioning a frequency of an output clock signal of the phase-locked loop from a first frequency to a target frequency responsive to detection of a catastrophic cycle slip event in the absence of an out-of-frequency event.
2. The method, as recited in claim 1 , wherein the catastrophic cycle slip event is detected responsive to a substantial frequency change of the input clock signal.
3. The method, as recited in claim 1 , wherein the catastrophic cycle slip event is detected responsive to the phase difference signal exceeding a predetermined number of update periods of the phase difference signal.
4. The method, as recited in claim 3 , further comprising:
comparing a value of the phase difference signal to the predetermined number of update periods of the phase difference signal; and
generating a catastrophic cycle slip detection signal based on the comparing.
5. The method, as recited in claim 1 , further comprising:
storing a value of the phase difference signal after the frequency of the output clock signal reaches the target frequency in response to the detection of the catastrophic cycle slip event; and
incrementally adjusting the phase difference signal and decrementing the stored value of the phase difference signal to gradually zero out a phase difference between the input clock signal and the feedback clock signal.
6. The method, as recited in claim 5 , further comprising:
resuming closed-loop operation after setting the phase difference signal to zero; and
detecting an additional cycle slip event in the absence of an out-of-frequency event and immediately after resuming the closed-loop operation.
7. The method, as recited in claim 1 , further comprising:
detecting the catastrophic cycle slip event based on the phase difference signal and a predetermined number of update periods of the phase difference signal.
8. The method, as recited in claim 1 , wherein the transitioning comprises:
calculating a target loop filter output value based on a next measured average input clock frequency; and
selectively ramping the loop filter output signal to the target loop filter output value based on a comparison of the target loop filter output value to the loop filter output signal.
9. The method, as recited in claim 8 , wherein the transitioning comprises:
zeroing the phase difference signal after the loop filter output signal achieves the target loop filter output value and before configuring the phase-locked loop for closed-loop operation.
10. A phase-locked loop comprising:
a phase detector configured to generate a phase difference signal based on an input clock signal and a feedback clock signal;
a monitor configured to detect a catastrophic cycle-slip event responsive to the phase difference signal and a predetermined number of update periods of the phase difference signal and in the absence of an out-of-frequency event; and
a change-limiting loop filter configured to adjust an output signal responsive to the catastrophic cycle-slip event.
11. The phase-locked loop, as recited in claim 10 , wherein the change-limiting loop filter is configured to ramp the output signal from a value associated with a first frequency of a phase-locked loop output signal to a target value associated with a target frequency of the phase-locked loop output signal responsive to a difference between the target frequency and the first frequency being greater than a predetermined frequency threshold.
12. The phase-locked loop, as recited in claim 10 , wherein the catastrophic cycle-slip event is detected responsive to a substantial frequency change of the input clock signal.
13. The phase-locked loop, as recited in claim 10 , further comprising:
a comparator configured to generate a catastrophic cycle slip detection signal based on a comparison of a value of the phase difference signal to the predetermined number of update periods of the phase difference signal.
14. The phase-locked loop, as recited in claim 10 , further comprising:
a counter configured to load a value of the phase difference signal after a frequency of the output signal reaches a target frequency in response to a detection of the catastrophic cycle-slip event and configured to decrement the value in response to incremental adjustment of the phase difference signal.
15. The phase-locked loop, as recited in claim 10 , wherein the monitor is further configured to detect the out-of-frequency event based on a frequency difference between a frequency of the input clock signal and a frequency threshold value.
16. The phase-locked loop, as recited in claim 15 , wherein the frequency difference is less than a threshold frequency difference for an out-of-frequency event.
17. The phase-locked loop, as recited in claim 10 , further comprising:
a first time-to-digital converter configured to generate a first digital signal indicative of a first frequency of the input clock signal; and
a second time-to-digital converter configured to generate a second digital signal indicative of a second frequency of the feedback clock signal,
wherein the monitor detects the absence of the out-of-frequency event based on the first digital signal, and
wherein the phase detector uses the first digital signal and the second digital signal to generate the phase difference signal.
18. The phase-locked loop, as recited in claim 10 , further comprising:
a time-to-digital converter configured to periodically generate a digital frequency signal; and
a comparator configured to generate an out-of-frequency signal based on another frequency-stable input clock signal and the digital frequency signal.
19. An apparatus for handling a frequency change of an input clock signal, the apparatus comprising:
means for detecting a catastrophic cycle slip event of a phase difference signal in the absence of an out-of-frequency event in a phase-locked loop; and
means for transitioning an output clock signal from a first frequency to a second frequency in response to detection of the catastrophic cycle slip event in the absence of an out-of-frequency event in the phase-locked loop.
20. The apparatus, as recited in claim 19 , further comprising:
means for gradually aligning a first phase of a feedback clock signal to a second phase of the input clock signal after transitioning the output clock signal from the first frequency to the second frequency.
21. The method, as recited in claim 1 , further comprising:
enabling a holdover mode of operating the phase-locked loop or switching a source of the input clock signal responsive to detection of the out-of-frequency event.