Using time-to-digital converters to delay signals with high accuracy and large range
A system delays input clock signals using time-to-digital converters (TDCs) to convert edges or the clock signals to digital values and storing the digital values in a memory. The digital values are retrieved from the memory based on a desired delay. A time counter used by the TDCs to determine the edges is also used determine the delay. The accuracy and range of the delay depends on the time counter and size of the memory.
1. A method of operating a phase-locked loop comprising:
with a first time-to-digital converter, converting first edges of a first clock signal to first digital values using output values of a counter circuit;
with a second time-to-digital converter, converting second edges of a second clock signal to second digital values using output values of the counter circuit;
with a third time-to-digital converter, converting third edges of a third clock signal to third digital values using output values of the counter circuit;
storing the first digital values and the second digital values in first and second queues within at least one memory;
outputting each respective value of the first digital values and the second digital values from the memory after a first period of delay elapses following storing the respective value in the memory; and
sequentially receiving and processing the first digital values and the second digital values output from the memory using a phase and frequency detector of the phase-locked loop.
2. The method of claim 1 wherein the first period of delay is programmable.
3. The method of claim 1 wherein the first clock signal is a reference clock signal supplied to the phase-locked loop, and the second clock signal is a feedback clock signal of the phase-locked loop.
4. The method of claim 1 wherein the first edges and the second edges are each rising edges or each falling edges.
5. The method of claim 1 further comprising switching from sequentially receiving and processing the first digital values and the second digital values output from the memory using the phase and frequency detector to sequentially receiving and processing the second digital values and the third digital values output from the memory using the phase and frequency detector.
6. The method of claim 5 wherein the first clock signal and the third clock signal are reference clock signals, and the second clock signal is a feedback clock signal.
7. A method of operating a phase-locked loop comprising:
with a first time-to-digital converter, converting first edges of a first clock signal to first digital values;
with a second time-to-digital converter, converting second edges of a second clock signal to second digital values;
with a third time-to-digital converter, converting third edges of a feedback clock signal to third digital values;
storing the first, second, and third digital values in first, second, and third queues within at least one memory coupled to the first, second, and third time-to-digital converters;
providing from the memory to a phase and frequency detector either each respective value of the first digital values or of the second digital values after a first period of delay elapses following storing the respective value in the memory; and
providing from the memory to the phase and frequency detector each respective value of the third digital values after the first period of delay elapses following storing the respective value in the memory.
8. The method of claim 7 further comprising determining a quality of one or both of the first clock signal and the second clock signal.
9. The method of claim 7 wherein providing from the memory to a phase and frequency detector either each respective value of the first digital values or of the second digital values after a first period of delay elapses following writing the respective value to the memory includes:
providing from the memory to the phase and frequency detector each respective value of the first digital values after a first period of delay elapses following writing the respective value to the memory; and
switching from providing from the memory to the phase and frequency detector each respective value of the first digital values to providing from the memory to the phase and frequency detector each respective value of the second digital values after a first period of delay elapses following writing the respective value to the memory.
10. The method of claim 9 further comprising determining a quality of the first clock signal, the switching being in response to the quality.
11. The method of claim 10 wherein determining the quality includes analyzing a frequency and phase of the first clock signal.
12. The method of claim 10 wherein the quality is lower quality than a quality of the second clock signal.
13. The method of claim 7 wherein the first period of delay is programmable.
14. A phase-locked loop comprising:
a counter circuit;
a first time-to-digital converter configured to sample output values of the counter circuit using edges of a first clock signal to output first digital values;
at least one memory coupled to the first time-to-digital converter and configured to store the first digital values in a queue within the memory;
compare circuitry configured, for each respective value of the first digital values stored in the queue within the memory, to compare a first input compare value that is based on the respective value to a second input compare value that is based on a current count value output by the counter circuit, and further configured to be responsive to the comparison indicating a match between the first input compare value and the second input compare value to (i) determine that a first period of delay has elapsed following the storing of the respective value in the queue and to (ii) output the respective value from the memory; and
a phase and frequency detector coupled to the memory and configured to sequentially receive and process the first digital values output from the memory.
15. The phase-locked loop of claim 14 wherein the first input compare value is the first digital value corresponding to the respective value adjusted by the first period of delay.
16. The phase-locked loop of claim 14 wherein the first input compare value is the first digital value corresponding to the respective value and the second input compare value is the current count value adjusted by the first period of delay.
17. The phase-locked loop of claim 14 wherein the first period of delay is programmable.
18. The phase-locked loop of claim 14 wherein the first clock signal is a reference clock signal supplied to the phase-locked loop or the first clock signal is a feedback clock signal of the phase-locked loop.
19. The phase-locked loop of claim 14 wherein the first and second edges are both rising edges or both falling edges.