Display apparatus

1. A display apparatus comprising:

a display panel including a plurality of first gate lines;

a first gate driver connected to first ends of the plurality of first gate lines;

a second gate driver connected to second ends of the plurality of first gate lines;

a feedback line connected adjacent to the first end of one of the plurality of first gate lines; and

a gate delay sensing circuit connected to the feedback line, wherein the gate delay sensing circuit comprises:

a time-to-digital converter which converts an activation time of a feedback gate signal into a digital activation value, wherein the feedback gate signal is retrieved from the feedback line when the first gate driver is enabled and the second gate driver is disabled or when the first gate driver is disabled and the second gate driver is enabled; and

a digital comparator which generates a digital delay value based on the digital activation value, wherein the digital delay value indicates a resistive-capacitive delay of the one of the plurality of first gate lines connected to the feedback line.

2. The display apparatus of claim 1 , wherein

the time-to-digital converter converts a first activation time of a first feedback gate signal into a first digital activation value by oversampling the first feedback gate signal, wherein the first feedback gate signal is retrieved from the feedback line when the first gate driver is enabled and the second gate driver is disabled, and

the time-to-digital converter converts a second activation time of a second feedback gate signal into a second digital activation value by oversampling the second feedback gate signal, wherein the second feedback gate signal is retrieved from the feedback line when the first gate driver is disabled and the second gate driver is enabled.

3. The display apparatus of claim 2 , wherein

the time-to-digital converter detects the first activation time and outputs a first bit periodically at a predetermined sampling cycle while a voltage level of the first feedback gate signal is higher than a reference voltage level, and

the time-to-digital converter detects the second activation time and outputs the first bit periodically at the sampling cycle while a voltage level of the second feedback gate signal is higher than the reference voltage level.

4. The display apparatus of claim 2 , wherein the digital comparator compares the first digital activation value with the second digital activation value to generate the digital delay value.

5. The display apparatus of claim 4 , wherein

each of the first digital activation value and the digital delay value is represented as a combination of first bits,

the second digital activation value is represented as a combination of the first bits and second bits, and

a number of the first bits included in the digital delay value is substantially equal to a difference between a number of the first bits included in the first digital activation value and a number of the first bits included in the second digital activation value.

6. The display apparatus of claim 2 , wherein the gate delay sensing circuit further includes:

a memory which stores the first digital activation value and the second digital activation value.

7. The display apparatus of claim 1 , wherein the gate delay sensing circuit is located inside the first gate driver.

8. The display apparatus of claim 1 , further comprising:

a timing controller configured to compensate the resistive-capacitive delay based on the digital delay value.

9. The display apparatus of claim 1 , wherein the one of the plurality of first gate lines connected to the feedback line is a dummy gate line.

10. The display apparatus of claim 1 , wherein the display panel further includes:

a plurality of pixels connected to the plurality of first gate lines; and

a plurality of data lines connected to the plurality of pixels.