Gate driver output protection circuit

1. A method for protecting a system including a driver integrated circuit, the method comprising:

receiving a driver input signal;

logically combining a logic signal with the driver input signal to generate an indication of whether a rising edge of the driver input signal is delayed in an output signal at an output node of the driver integrated circuit coupled to a terminal of the driver integrated circuit, the logic signal being asserted in response to completion of a corresponding rising edge of the output signal;

logically combining a second logic signal with the driver input signal to generate a second indication of whether a falling edge of the driver input signal is delayed in the output signal at the output node, the second logic signal being asserted in response to completion of a corresponding falling edge of the output signal;

generating an error signal based on the indication and the second indication, ; and

driving the output signal externally to the driver integrated circuit, the output signal being driven based on the driver input signal and the error signal.

2. The method as recited in claim 1 further comprising:

generating the indication of the delay based on a counter value corresponding to the delay; and

incrementing the counter value in response to a transition of the driver input signal in the absence of a corresponding transition of the output signal.

3. The method as recited in claim 1 further comprising:

generating the indication of the delay based on a counter value corresponding to an estimate of a long-term average of the delay;

incrementing the counter value by a first predetermined amount in response to a transition of the driver input signal in the absence of a corresponding transition of the output signal; and

decrementing the counter value by a second predetermined amount in a predetermined interval.

4. The method as recited in claim 1 further comprising detecting an error condition based on the indication of the delay and a predetermined threshold and generating the error-signal based thereon.

5. The method as recited in claim 4 wherein the error signal indicates whether the error condition occurred in response to the output signal rising from a first voltage level to a second voltage level or in response to the output signal falling from the second voltage level to the first voltage level.

6. The method as recited in claim 1 wherein driving the output signal includes configuring an output driver to enter a safer output state for a predetermined interval in response to detecting an error condition based on the indication of the delay.

7. The method as recited in claim 6 wherein driving the output signal further includes transitioning from the safer output state to a normal state in response to expiration of the predetermined interval in the safer output state.

8. The method as recited in claim 6 wherein the output driver is configured to transition to the safer output state from a second safer output state and in response to a second expiration of a second predetermined interval in the second safer output state, and driving the output signal further comprises transitioning to the second safer output state from a normal output state.

9. The method as recited in claim 6 wherein in the safer output state, an output device of the output driver is configured in a strong pull-down configuration or a weak pull-down configuration, the output driver being configured in the weak pull-down configuration from the strong pull-down configuration after a predetermined period of time.

10. The method as recited in claim 1 wherein the output signal is driven further based on a second indication of a sensed temperature of the driver integrated circuit, and the method further comprises:

generating the second indication based on the sensed temperature of a die of the driver integrated circuit; and

configuring an output driver to enter a safer output state in response to the second indication exceeding a predetermined threshold.

11. The method as recited in claim 1 further comprising:

asserting the logic signal in response to completion of the rising edge of an output signal at the output node of the driver integrated circuit coupled to the terminal of the driver integrated circuit, the logic signal being deasserted otherwise; and

asserting the second logic signal in response to completion of the falling edge of the output signal, the second logic signal being deasserted otherwise.

12. An integrated circuit for controlling a high-power drive device, the integrated circuit comprising:

a driver circuit configured to drive an output signal to a terminal of the integrated circuit, the output signal being driven based on a driver input signal and an error signal; and

a logic circuit configured to generate the error signal based on a first logical combination of a logic signal and the driver input signal indicating whether a rising edge of the driver input signal is delayed in the output signal and a second logical combination of a second logic signal and the driver input signal indicating whether a falling edge of the driver input signal is delayed in the output signal, the logic signal being asserted in response to completion of a corresponding rising edge of the output signal, and the second logic signal being asserted in response to completion of a corresponding falling edge of the output signal.

13. The integrated circuit as recited in claim 12 wherein the logic circuit comprises a counter circuit configured to increment a counter value corresponding to the delay in response to a transition of the driver input signal in the absence of a corresponding transition of the output signal, the indication of the delay being based on the counter value.

14. The integrated circuit as recited in claim 12 wherein the logic circuit is further configured to detect an error condition based on the indication of the delay and a predetermined threshold, and further configured to indicate whether the error condition occurred in response to the output signal rising from a first voltage level to a second voltage level or in response to the output signal falling from the second voltage level to the first voltage level.

15. The integrated circuit as recited in claim 12 wherein the logic circuit is configured to cause an output driver to enter a safer output state for a predetermined interval in response to detecting an error condition based on the indication of the delay.

16. The integrated circuit as recited in claim 15 wherein the logic circuit is further configured to transition the output driver from the safer output state to a normal state in response to expiration of the predetermined interval in the safer output state and no other error condition being detected.

17. The integrated circuit as recited in claim 15 wherein the logic circuit is further configured to transition the output driver to the safer output state from a second safer output state and in response to a second expiration of a second predetermined interval in the second safer output state, and driving the output signal further comprises transitioning to the second safer output state from a normal output state.

18. The integrated circuit as recited in claim 15 wherein in the safer output state, an output device of the output driver is configured in a strong pull-down configuration or a weak pull-down configuration, the output driver being configured in the weak pull-down configuration from the strong pull-down configuration after a predetermined period of time.

19. The integrated circuit as recited in claim 12 further comprising a temperature sensor configured to sense a temperature of the integrated circuit, the output signal being driven further based on a second indication, and the logic circuit being configured to generate the second indication based on a sensed temperature of the integrated circuit and to cause an output driver to enter a safer output state in response to the second indication exceeding a predetermined threshold.

20. An integrated circuit for controlling a high-power drive device, the integrated circuit comprising:

a driver circuit configured to drive an output signal to a terminal of the integrated circuit, the output signal being driven based on a driver input signal and an error signal; and

a logic circuit configured to generate the error signal based on an indication of a delay between receipt of an edge of the driver input signal and arrival of a corresponding edge of the output signal at an output node of the integrated circuit coupled to the terminal, the logic circuit comprising a counter circuit configured to add a first predetermined value to a counter value corresponding to an estimate of a long-term average of the delay in response a transition of the driver input signal in the absence of a corresponding transition of the output signal, and configured to subtract a second predetermined value from the count value in a predetermined interval, the indication of the delay being based on the counter value.

21. The integrated circuit as recited in claim 20 wherein the logic circuit is configured to cause an output driver to enter a safer output state for a predetermined interval in response to detecting an error condition based on the indication of the delay, in the safer output state, an output device of the output driver is configured in a strong pull-down configuration or a weak pull-down configuration, the output driver being configured in the weak pull-down configuration from the strong pull-down configuration after a predetermined period of time.