Resistor based delta sigma multiplying DAC with integrated reconstruction filter

1. An apparatus comprising:

a phase-locked loop including a digital loop filter to supply a digital control signal;

a digital to analog converter including,

a delta sigma modulator coupled to receive the digital control signal from the digital loop filter and supply digital data after processing the digital control signal;

a multi-bit digital to analog converter (DAC) with unit elements coupled to receive the digital data from the delta sigma modulator;

an amplifier stage coupled to the multi-bit DAC;

a first low pass filter coupled between the multi-bit DAC and the amplifier stage; and

a second low pass filter coupled to an output of the amplifier stage and coupled to supply an analog signal.

2. The apparatus as recited in claim 1 wherein the first low pass filter is a first order filter.

3. The apparatus as recited in claim 2 wherein the second low pass filter is a higher order filter.

4. The apparatus as recited in claim 1 wherein the amplifier stage includes a chopped amplifier.

5. The apparatus as recited in claim 1 further comprising:

a voltage controlled crystal oscillator (VCXO) coupled to the analog signal and configured to supply a VCXO output signal according to the analog signal.

6. The apparatus as recited in claim 5 further comprising:

a phase and frequency detector coupled to receive the VCXO output signal.

7. The apparatus as recited in claim 1 , wherein the multi-bit DAC uses resistors as the unit elements.

8. The apparatus as recited in claim 7 wherein the resistors supply a current to the amplifier stage indicative of the digital data from the delta sigma modulator.

9. The apparatus as recited in claim 1 further comprising:

a first resistor and a second resistor coupled in series between a power supply node and ground, a node between the first and second resistors coupled to an amplifier of the amplifier stage;

wherein at least one of the first and second resistors is variable to allow adjustment of a common mode resistor ratio to thereby provide offset control; and

a variable feedback resistor in the amplifier stage coupled between an output of the amplifier stage and a second input to the amplifier stage, a value of the variable feedback resistor controlling gain of the amplifier stage.

10. A method comprising:

generating a digital loop filter output signal in a digital loop filter of a phase-locked loop;

supplying the digital loop filter output signal to a delta sigma modulator;

generating a delta sigma modulator output signal based on the digital loop filter output signal;

supplying the delta sigma modulator output signal to a multi-bit digital to analog converter (DAC);

converting the delta sigma modulator output signal supplied to the multi-bit DAC to a first analog signal;

filtering the first analog signal to remove high frequency components from the first analog signal in a first low pass filter and generating a filtered first analog signal and supplying the filtered first analog signal to an amplifier stage;

providing gain to the filtered first analog signal in an amplifier stage and supplying a second analog signal from the amplifier stage; and

filtering the second analog signal from the amplifier stage in a second low pass filter and supplying from the second low pass filter an output analog signal.

11. The method as recited in claim 10 further comprising using chopping in the amplifier stage to reduce device flicker noise.

12. The method as recited in claim 10 wherein the first low pass filter is a first order filter.

13. The method as recited in claim 12 wherein the second low pass filter is a higher order filter.

14. The method as recited in claim 10 further comprising:

supplying the output analog signal to a voltage controlled crystal oscillator (VCXO) and generating a VCXO output signal according to the output analog signal.

15. The method as recited in claim 14 further comprising:

supplying a feedback divider with the VCXO output signal.

16. An apparatus comprising:

an integrated circuit including,

a phase-locked loop including,

a phase and frequency detector;

a digital loop filter coupled to the phase and frequency detector and supplying a digital control signal;

a digital to analog converter including,

a delta sigma modulator coupled to receive the digital control signal;

a multi-bit digital to analog converter (DAC) coupled to receive an output of the delta sigma modulator;

an amplifier stage coupled to the multi-bit digital to analog converter;

a first low pass filter coupled between the multi-bit digital to analog converter and the amplifier stage; and

a second low pass filter coupled to an output of the amplifier stage to supply an analog signal corresponding to the digital control signal; and

a voltage controlled crystal oscillator coupled to the analog signal to supply a voltage controlled crystal oscillator output signal based on the analog signal.

17. The apparatus as recited in claim 16 wherein the multi-bit DAC comprises resistors as unit elements.

18. The apparatus as recited in claim 17 wherein the resistors supply a current to the amplifier stage indicative of the output of the delta sigma modulator.

19. The apparatus as recited in claim 16 further comprising a feedback divider of the phase-locked loop coupled to an output of the voltage controlled crystal oscillator.

20. The apparatus as recited in claim 16 further comprising:

a first resistor and a second resistor coupled in series between a power supply node and a ground node, a node between the first and second resistors coupled to an input of an amplifier of the amplifier stage;

wherein at least one of the first and second resistors is variable to allow adjustment of a common mode resistor ratio to thereby provide offset control for the amplifier stage; and

a variable feedback resistor in the amplifier stage coupled to a second input of the amplifier, a value of the variable feedback resistor controlling gain of the amplifier stage.