Systems and methods for controlling integrated circuit operation with below ground pin voltage
View Patent ↗Systems and methods for controlling operation of an integrated circuit by applying below ground voltage to one or more pins of the integrated circuit, and in which the application of a below ground pin voltage may be employed as an initiator of (or condition for) a given mode of circuit operation in a manner that prevents the inadvertent initiation of the given mode of operation that may otherwise occur due to accidental application of an above ground voltage to one or more pins of the integrated circuit.
1. Integrated circuitry, comprising:
operation control circuitry configured to provide an operation control signal to initiate an operation mode; and
a first external pin coupled to the operation control circuitry and configured to receive an externally applied voltage; and
voltage sensing circuitry configured to detect the presence of an externally applied voltage received at the first external pin that is below circuit ground;
wherein the operation control circuitry is configured to provide the operation control signal only upon detection by the voltage sensing circuitry of the application of the below ground voltage to the first external pin.
2. Integrated circuitry, comprising:
operation control circuitry configured to provide an operation control signal to initiate an operation mode; and
a first external pin coupled to the operation control circuitry and configured to receive an externally applied voltage;
wherein the operation control circuitry is configured to provide the operation control signal upon application of a below ground voltage to the first external pin; and
further comprising voltage sensing circuitry coupled between the first external pin and the operation control circuitry, the voltage sensing circuitry being configured to sense the presence of a voltage present on the first external pin that meets a pre-defined voltage threshold that is below circuit ground; and to provide a signal to the operation control circuitry that is indicative of the presence of the applied voltage on the first external pin that meets the pre-defined below ground threshold.
3. Integrated circuitry, comprising:
operation control circuitry configured to provide an operation control signal to initiate an operation mode; and
a first external pin coupled to the operation control circuitry and configured to receive an externally applied voltage;
wherein the operation control circuitry is configured to provide the operation control signal upon application of a below ground voltage to the first external pin; and
where the circuitry further comprises:
processing circuitry configured to enable the operation mode by providing an operation enable signal to the operation control circuitry, and
wherein the operation control circuitry is configured to provide the operation control signal only when the operation enable signal is provided to the operation control circuitry by the at least one processing circuitry at the same time as application of a below ground voltage to the first external pin.
4. The circuitry of claim 3 , further comprising a non-volatile memory (NVM) device coupled to receive programming data from the processing circuitry and being coupled to receive the operation control signal from the operation control circuitry; wherein the operation mode comprises programming of the NVM device; and wherein the processing circuitry is configured to provide the operation enable signal to the operation control circuitry at the same time the programming data is provided to the NVM device.
5. The circuitry of claim 4 , further comprising:
a second external pin coupled to the operation control circuitry and to the NVM device, the second external pin being configured to receive an externally applied programming voltage for programming the NVM device, and the programming voltage being greater than a power supply voltage provided to the integrated circuitry;
wherein the operation control circuitry is configured to provide the operation control signal only when the operation enable signal is provided to the operation control circuitry by the at least one processing circuitry at the same time as application of a below ground voltage to the first external pin and application of the programming voltage to the second external pin.
6. The circuitry of claim 5 , further comprising:
a switch device coupled between the second external pin and the NVM device, the switch device coupled to receive the operation control signal from the operation control circuitry and to selectively conduct the programming voltage to the NVM device in response to the operation control signal; and
programming voltage sensing circuitry coupled between the second external pin and the operation control circuitry, the programming voltage sensing circuitry being configured to sense the presence of the programming voltage on the first external pin; and to provide a signal to the operation control circuitry that is indicative of the presence of the programming voltage on the second external pin;
wherein the operation control circuitry is configured to provide the operation control signal only when the operation enable signal is provided to the operation control circuitry by the at least one processing circuitry at the same time as at least the following two signals are provided:
a signal from the voltage sensing circuitry to the operation control circuitry that is indicative of the presence of the applied below ground voltage on the first external pin, and
a signal from the programming voltage sensing circuitry to the operation control circuitry that is indicative of the presence of the programming voltage on the second external pin.
7. The circuitry of claim 5 , further comprising:
a third external pin coupled to the operation control circuitry, the third external pin being configured to receive an externally applied power supply voltage provided to the integrated circuitry;
wherein the operation control circuitry is configured to provide the operation control signal only when the operation enable signal is provided to the operation control circuitry by the at least one processing circuitry at the same time as application of a below ground voltage to the first external pin, application of the programming voltage to the second external pin, and application of the power supply voltage to the third external pin.
8. The circuitry of claim 7 , further comprising:
a switch device coupled between the second external pin and the NVM device, the switch device coupled to receive the operation control signal from the operation control circuitry and to selectively conduct the programming voltage to the NVM device in response to the operation control signal;
programming voltage sensing circuitry coupled between the second external pin and the operation control circuitry, the programming voltage sensing circuitry being configured to sense the presence of the programming voltage on the first external pin; and to provide a signal to the operation control circuitry that is indicative of the presence of the programming voltage on the second external pin; and
power supply voltage sensing circuitry between the third external pin and the operation control circuitry, the power supply voltage sensing circuitry being configured to sense the presence of the power supply voltage on the third external pin; and to provide a signal to the operation control circuitry that is indicative of the presence of the power supply voltage on the third external pin;
wherein the operation control circuitry is configured to provide the operation control signal only when the operation enable signal is provided to the operation control circuitry by the at least one processing circuitry at the same time as at least the following three signals are provided:
a signal from the voltage sensing circuitry to the operation control circuitry that is indicative of the presence of the applied below ground voltage on the first external pin,
a signal from the programming voltage sensing circuitry to the operation control circuitry that is indicative of the presence of the programming voltage on the second external pin, and
a signal from the power supply voltage sensing circuitry to the operation control circuitry that is indicative of the presence of the power supply voltage on the third external pin.
9. The circuitry of claim 4 , wherein the NVM device is a one time programmable (OTP) memory device.
10. The circuitry of claim 4 , wherein the integrated circuitry comprises a portion of a general purpose circuit; and wherein the programming data comprises software and settings of a dedicated purpose for the general purpose circuit.
11. A method of controlling an operation mode of an integrated circuit, comprising:
sensing for the presence of an externally applied below ground voltage on a first external pin of the integrated circuit; and
initiating an operation mode of the integrated circuit only upon detection of the application of a below ground voltage on the first external pin of the integrated circuit.
12. A method of controlling an operation mode of an integrated circuit, comprising:
sensing for the presence of an externally applied below ground voltage on a first external pin of the integrated circuit; and
providing an operation control signal to initiate an operation mode of the integrated circuit upon application of a below ground voltage on the first external pin of the integrated circuit; and
where the method further comprises sensing for the presence of an externally applied below ground voltage on the first external pin of the integrated circuit that meets a pre-defined voltage threshold that is below circuit ground; and providing the operation control signal to initiate the operation mode in response to the receipt of the operation enable signal from the at least one processing circuitry only when the externally applied below ground voltage meeting the pre-defined voltage threshold is present at the first external pin of the integrated circuit at the same time that the operation enable signal is received.
13. A method of controlling an operation mode of an integrated circuit, comprising:
sensing for the presence of an externally applied below ground voltage on a first external pin of the integrated circuit; and
providing an operation control signal to initiate an operation mode of the integrated circuit upon application of a below ground voltage on the first external pin of the integrated circuit; and
where the method further comprises:
receiving an operation enable signal from at least one processing circuitry, the operation enable signal for enabling the operation mode of the integrated circuit, and
providing the operation control signal to initiate the operation mode in response to the receipt of the operation enable signal from the at least one processing circuitry only when the externally applied below ground voltage is present at the first external pin of the integrated circuit at the same time that the operation enable signal is received.
14. The method of claim 13 , wherein the integrated circuit comprises a non-volatile memory (NVM) device configured to receive programming data; and wherein the method further comprises receiving the operation enable signal from the processing circuitry at the same time that programming data is provided to the NVM device.
15. The method of claim 14 , further comprising:
sensing for the presence of an externally applied NVM programming voltage at a second external pin of the integrated circuit, the programming voltage being greater than a power supply voltage provided to the integrated circuit; and
providing the operation control signal only when the operation enable signal is received from the at least one processing circuitry simultaneously with presence of the below ground voltage at the first external pin and presence of the programming voltage at the second external pin.
16. The method of claim 15 , further comprising:
providing a switch device coupled between the second external pin and the NVM device, the switch device coupled to receive the operation control signal and to selectively conduct the programming voltage to the NVM device in response to the operation control signal; and
sensing for the presence of the programming voltage on the second external pin; and
providing the operation control signal to cause the switch device to conduct the programming voltage to the NVM device only when the operation enable signal is received from the at least one processing circuitry simultaneously with presence of the below ground voltage on the first external pin, and presence of the programming voltage on the second external pin.
17. The method of claim 16 , further comprising:
sensing for the presence of an externally applied power supply voltage at a third external pin of the integrated circuit; and
providing the operation control signal only when the operation enable signal is received from the at least one processing circuitry simultaneously with the presence of the applied below ground voltage on the first external pin, presence of the programming voltage on the second external pin, and presence of the power supply voltage on the third external pin.
18. The method of claim 17 , further comprising:
providing a switch device coupled between the second external pin and the NVM device, the switch device coupled to receive the operation control signal and to selectively conduct the programming voltage to the NVM device in response to the operation control signal;
sensing for the presence of the programming voltage on the second external pin;
sensing for the presence of the power supply voltage on the third external pin; and
providing the operation control signal to cause the switch device to conduct the programming voltage to the NVM device only when the operation enable signal is received from the at least one processing circuitry simultaneously with the presence of the applied voltage on the first external pin, presence of the programming voltage on the second external pin, and presence of the power supply voltage on the third external pin.
19. The method of claim 14 , wherein the NVM device is a one time programmable (OTP) memory device.
20. The method of claim 14 , wherein the integrated circuit comprises a portion of a general purpose circuit; and wherein the programming data comprises software and settings of a dedicated purpose for the general purpose circuit.