Use of a virtual clock in a PLL to maintain a closed loop system

1. A method comprising:

using a virtual clock signal as a reference clock signal for a phase-locked loop, the virtual clock signal being time stamps separated by a time period, the time stamps corresponding to respective transitions of the virtual clock signal; and

using the virtual clock signal as the reference clock signal in holdover mode responsive to a loss of signal of an input reference clock signal.

2. The method as recited in claim 1 further comprising:

generating an edge of the virtual clock signal based on an edge of a feedback clock signal.

3. The method as recited in claim 2 further comprising:

determining a period of the virtual clock signal based on a difference in time stamps between successive edges of the feedback clock signal.

4. The method as recited in claim 1 further comprising:

determining a period of the virtual clock signal based on a nominal period value stored in an integrated circuit in which the phase-locked loop is disposed.

5. A method comprising:

using a virtual clock signal as a reference clock signal for a phase-locked loop, the virtual clock signal being time stamps separated by a time period, the time stamps corresponding to respective transitions of the virtual clock signal; and

using the virtual clock signal as the reference clock signal responsive to a startup condition.

6. The method as recited in claim 5 comprising:

stopping using the virtual clock signal as the reference clock signal responsive to availability of an input reference clock signal.

7. The method as recited in claim 1 further comprising:

while using the virtual clock signal as the reference clock signal, modulating a phase of an output of the phase-locked loop by adjusting a divide value of a feedback divider of the phase-locked loop.

8. A phase-locked loop comprising:

a virtual clock signal generator to supply a virtual clock signal, the virtual clock signal being a series of time stamps separated by a time period, the time stamps corresponding to respective transitions of the virtual clock signal; and

a selector circuit to select as a reference clock signal for use by a phase and frequency detector of the phase-locked loop the virtual clock signal instead of a second reference clock signal, the second reference clock signal being based on an input reference clock signal.

9. The phase-locked loop as recited in claim 8 ,

wherein the phase and frequency detector is coupled to receive the reference clock signal and a feedback clock signal; and

wherein the selector circuit is responsive to a loss of signal of the input reference clock signal to use the virtual clock signal as the reference clock signal.

10. The phase-locked loop as recited in claim 9 wherein, the virtual clock signal generator is configured to determine a period of the reference clock signal based on a period of the feedback clock signal.

11. The phase-locked loop as recited in claim 9 wherein, the virtual clock signal generator is configured to generate an edge of the virtual clock signal based on an edge of the feedback clock signal.

12. The phase-locked loop as recited in claim 9 wherein the reference clock signal is supplied as a digital reference clock signal and the feedback clock signal is supplied as a digital feedback signal, the digital reference clock signal being a time stamp associated with a transition of an analog reference clock signal when the second reference clock signal is selected as the reference clock signal, and the digital feedback signal being another time stamp associated with a transition of an analog feedback clock signal.

13. The phase-locked loop as recited in claim 12 further comprising:

a time to digital converter to convert the analog feedback clock signal to the digital feedback signal.

14. The phase-locked loop as recited in claim 8 wherein

the phase and frequency detector is coupled to receive the reference clock signal and a feedback signal; and

wherein the selector circuit is responsive to a loss of signal of the input reference clock signal to select the virtual clock signal instead of the second reference clock signal as the reference clock signal.

15. The phase-locked loop as recited in claim 8 wherein,

the virtual clock signal generator generates the virtual clock signal with a period based on a nominal period value stored in an integrated circuit in which the phase-locked loop is disposed.

16. The phase-locked loop as recited in claim 8 wherein, the selector circuit selects the virtual clock signal as the reference clock signal responsive to a startup condition.

17. The phase-locked loop as recited in claim 8 wherein, the selector circuit selects the second reference clock signal as the reference clock signal responsive to availability of the input reference clock signal.

18. The phase-locked loop as recited in claim 8 further comprising:

a feedback divider circuit; and

wherein the phase-locked loop is configured to modulate a phase of an output of the phase-locked loop through the feedback divider circuit while using the virtual clock signal as the reference clock signal.

19. An apparatus comprising:

a virtual clock signal generator to supply a virtual clock signal, the virtual clock signal being a series of digital values separated by a time period, the digital values indicating respective transitions of the virtual clock signal;

a selector circuit to select as a digital reference clock signal the virtual clock signal in a first mode and to select a second digital reference clock signal in a second mode;

a phase and frequency detector (PFD) coupled to receive the digital reference clock signal and a digital feedback signal and supply a PFD output signal indicative of a difference between the digital reference clock signal and the digital feedback signal;

a loop filter coupled to an output of the phase and frequency detector to generate a loop filter output signal;

an oscillator to generate an oscillator output signal and coupled to the loop filter output signal; and

a feedback divider coupled to the oscillator output signal.

20. The apparatus as recited in claim 19 wherein a phase of the oscillator output signal is controlled during holdover by adjusting a divide value of the feedback divider.

21. The apparatus as recited in claim 19 wherein the first mode is holdover or startup and the second mode is normal operation.

22. The method as recited in claim 1 wherein the time period corresponds to a period of the virtual clock signal.