Jitter self-test using timestamps

1. A method for estimating jitter of a clock-signal-under-test, the method comprising:

generating a phase-adjusted clock signal based on an input clock signal and a feedback clock signal using a frequency-divided clock signal;

sweeping a phase of the clock-signal-under-test from a first predetermined phase to a second predetermined phase using P phase adjustments of the phase-adjusted clock signal;

generating N digital time codes for each phase adjustment of the P phase adjustments using a reference clock signal, each digital time code of the N digital time codes corresponding to a first edge of a clock signal based on the phase-adjusted clock signal, P being a first integer greater than zero and N being a second integer greater than zero;

estimating a standard deviation based on the N digital time codes for each of the P phase adjustments to generate an estimated standard deviation;

generating a jitter estimate based on the estimated standard deviation; and

generating a jitter indicator based on an expected period of the clock signal and the jitter estimate.

2. The method as recited in claim 1 wherein the phase-adjusted clock signal is a frequency-divided output of a phase-locked loop, a frequency-divided feedback signal of the phase-locked loop, or a frequency-divided input of the phase-locked loop.

3. The method as recited in claim 1 wherein the estimating comprises associating each digital time code of the N digital time codes for each phase adjustment of the P phase adjustments with a first set or a second set using the expected period.

4. The method as recited in claim 1 further comprising

estimating the expected period of the phase-adjusted clock signal.

5. The method as recited in claim 1 wherein the input clock signal is the reference clock signal and the clock signal is an output of a voltage-controlled oscillator of a phase-locked loop.

6. The method as recited in claim 1

wherein the first predetermined phase is zero and the second predetermined phase is a maximum phase.

7. The method as recited in claim 3 further comprising:

generating a variance based on digital time codes associated with the first set; and

generating the standard deviation based on the variance.

8. The method as recited in claim 3 wherein the estimating further comprises providing an indicator of the jitter estimate to a terminal of an integrated circuit.

9. The method as recited in claim 3 further comprising for a p th phase adjustment of the P phase adjustments:

associating an initial digital time code of the N digital time codes with the first set;

associating each other digital time code of the N digital time codes with the first set if the other digital time code equals a sum of the initial digital time code and a product of p and the expected period, where p corresponds to an index of the P phase adjustments and 0≤p≤P; and

associating each other digital time code of the N digital time codes with the second set if the other digital time code is not equal to the sum of the initial digital time code and the product of p and the expected period.

10. An integrated circuit for estimating jitter of a clock signal, the integrated circuit comprising:

a clock generator circuit configured to generate a phase-adjusted clock signal based on an input clock signal and a feedback clock signal;

a time-to-digital converter circuit configured to generate digital time codes corresponding to first edges of the clock signal using a reference clock signal;

a control circuit configured to sweep a phase of the clock signal from a first predetermined phase to a second predetermined phase using P phase adjustments applied to the clock generator circuit and configured to cause the time-to-digital converter circuit to generate N digital time codes for each phase adjustment of the P phase adjustments, P being a first integer greater than zero and N being a second integer greater than zero; and

a logic circuit configured to estimate a standard deviation based on the N digital time codes for each of the P phase adjustments to generate an estimated standard deviation, generate a jitter estimate based on the estimated standard deviation, and generate a jitter indicator based on an expected period of the clock signal and the jitter estimate.

11. The integrated circuit as recited in claim 10 wherein the clock generator circuit comprises a frequency divider circuit, and the phase adjustment is applied by the frequency divider circuit, the frequency divider circuit being an output divider circuit of a phase-locked loop, a feedback divider circuit of the phase-locked loop, or an input divider circuit of the phase-locked loop.

12. The integrated circuit as recited in claim 10 wherein the logic circuit is configured to associate, for each phase adjustment of the P phase adjustments, each digital time code of the N digital time codes with a first set or a second set using the expected period of the clock signal.

13. The integrated circuit as recited in claim 10 further comprising a frequency monitor circuit configured to generate the expected period of the phase-adjusted clock signal.

14. The integrated circuit as recited in claim 10 wherein the clock generator circuit comprises a phase-locked loop and the time-to-digital converter circuit is coupled to a feedback divider circuit of the phase-locked loop or an input divider circuit of the phase-locked loop.

15. The integrated circuit as recited in claim 10 wherein the input clock signal is the reference clock signal and the clock signal is an output of a voltage-controlled oscillator of the clock generator circuit.

16. The integrated circuit as recited in claim 10 wherein the reference clock signal is based on an output of a voltage-controlled oscillator of the clock generator circuit and the clock signal is the input clock signal.

17. The integrated circuit as recited in claim 12 further comprising a variance calculating circuit configured to generate a variance based on digital time codes associated with the first set, the jitter indicator being based on the variance.

18. The integrated circuit as recited in claim 12 wherein for a p th phase adjustment of the P phase adjustments, the logic circuit associates an initial digital time code of the N digital time codes with the first set, the logic circuit associates each other digital time code of the N digital time codes with the first set if the other digital time code equals a sum of the initial digital time code and a product of p and the expected period, where p corresponds to an index of the P phase adjustments and 0≤p≤P, and the logic circuit associates each other digital time code of the N digital time codes with the second set if the other digital time code is not equal to the sum of the initial digital time code and the product of p and the expected period.

19. An apparatus comprising:

means for generating an output clock signal based on an input clock signal and a feedback clock signal;

means for sweeping a phase of a clock-signal-under-test from a first predetermined phase to a second predetermined phase using P phase adjustments applied to the means for generating the output clock signal, P being a first integer greater than zero and N being a second integer greater than zero; and

means for estimating a standard deviation based on the N digital time codes for each of the P phase adjustments to generate an estimated standard deviation, generating a jitter estimate based on the estimated standard deviation, and generating a jitter indicator based on an expected period of a phase-adjusted clock signal based on the output clock signal and the jitter estimate, P being a first integer greater than zero and N being a second integer greater than zero.

20. The apparatus as recited in claim 19 wherein the input clock signal is a reference clock signal and the jitter indicator corresponds to a clock signal internal to the means for generating the output clock signal.