Managed timing engine

1. A method, comprising operating a managed timing engine that provides

a physical-layer timing output aligned to a physical-layer input timing reference using a phase locked loop, the physical-layer input timing reference selected from a multiplicity of physical-layer input timing references, and

a packet-based clock providing timing outputs synchronized to a packet-layer input timing reference,

wherein the managed timing engine has programmable multipier ratios for each of the physical-layer references,

wherein a time-stamping clock in the packet-based clock is derived from a physical-layer clock,

wherein the packet-based clock timing outputs include a 1-PPS signal with a programmable delay offset and

wherein at least one of the multiplicity of physical-layer input timing references that are not selected is measured against the physical-layer input timing reference that is selected using a digital phase lock loop where divider and multiplier factors are chosen to generate two nominal comparison frequency versions that are compared using a clock phase comparator and a phase differences signal is filtered to generate a correction term for a programmable multiplier.

2. The method of claim 1 , wherein the packet-based clock timing outputs include a frequency output, and further comprising controlling the time-stamping clock by steering the physical-layer clock with frequency corrections derived from the packet-based clock.

3. The method of claim 1 , further comprising supporting multiple timing domains by providing another timing output synchronized to another input reference selected from the multiplicity of physical-layer input timing references.

4. The method of claim 1 , further comprising providing multiple rates that are different by a small frequency offset.

5. The method of claim 1 , further comprising providing a programmable delay.

6. The method of claim 1 , further comprising measuring frequency offset.

7. The method of claim 1 , further comprising using another time-stamping clock derived from the physical-layer clock without steering and with frequency corrections derived from the packet-based clock applied as a mathematical correction to time-stamps developed in a time-stamper.

8. The method of claim 1 wherein the packet-based clock timing outputs include a 1 pulse-per-second (1 PPS) output with a Time-of-Day (TOD) message indicating a time at a 1 PPS event.

9. An apparatus, comprising a managed timing engine that includes

a primary timing output aligned to a selected input timing reference using a phase locked loop, the selected input timing reference selected from a multiplicity of input timing references and

a packet-based clock providing timing outputs synchronized to a packet-layer input timing reference,

wherein the managed timing engine includes a divider circuit having a programmable multiplier ratio,

wherein a time-stamping clock in the packet-based clock is derived from a physical-layer clock

wherein the packet-based clock timing outputs include a 1-PPS signal with a programmable delay offset and

wherein at least one of the multiplicity of physical-layer input timing references that are not selected is measured against the physical-layer input timing reference that is selected using a digital phase lock loop where divider and multiplier factors are chosen to generate two nominal comparison frequency versions that are compared using a clock phase comparator and a phase differences signal is filtered to generate a correction term for a programmable multiplier.

10. A method, comprising operating a managed timing engine that provides

a physical-layer timing output aligned to a physical-layer input timing reference using a phase locked loop, the physical-layer input timing reference selected from a multiplicity of physical-layer input timing references and

a packet-based clock providing timing outputs synchronized to a time input reference,

wherein the managed timing engine has programmable multiplier ratios for each of the physical-layer references,

wherein the time-stamping clock in the packet-based clock is derived from a physical-layer clock

wherein the packet-based clock timing outputs include a 1-PPS signal with a programmable delay offset and

wherein at least one of the multiplicity of physical-layer input timing references that are not selected is measured against the physical-layer input timing reference that is selected using a digital phase lock loop where divider and multiplier factors are chosen to generate two nominal comparison frequency versions that are compared using a clock phase comparator and a phase differences signal is filtered to generate a correction term for a programmable multiplier.

11. The method of claim 10 , including controlling the time-stamping clock by steering the physical-layer clock with frequency corrections derived from the packet-based clock.

12. The method of claim 10 , further comprising using another time-stamping clock derived from the physical-layer clock without steering and with frequency corrections derived from the packet-based clock applied as a mathematical correction to time-stamps developed in a time-stamper.

13. The method of claim 10 wherein the packet-based clock timing outputs include a 1 pulse-per-second (1 PPS) output with a Time-of-Day (TOD) message indicating a time at a 1 PPS event.

14. The method of claim 10 wherein the packet-based clock timing outputs include packet timing signals including PTP and/or NTP.