Buried word line memory integrated circuit system
View Patent ↗An integrated circuit system includes providing a semiconductor substrate and forming buried word lines in the semiconductor substrate with the buried word lines including vertical charge-trapping dielectric layers. The system further includes forming bit lines further comprising forming in-substrate portions in the semiconductor substrate, and forming above-substrate portions over the semiconductor substrate.
1. An integrated circuit system, comprising:
a semiconductor substrate;
buried word lines in the semiconductor substrate, the buried word lines including vertical charge-trapping dielectric layers;
bit lines further comprising:
in-substrate portions in the semiconductor substrate, and
above-substrate portions over the semiconductor substrate; and
conductive channels between the bit lines that are adjacent to the charge-trapping dielectric layers.
2. The system as claimed in claim 1 , further comprising the buried word lines and the bit lines connected for single-density or double-density mode operation.
3. The system as claimed in claim 1 , wherein the buried word lines further comprise:
conductive layers on the vertical charge-trapping dielectric layers; and
top dielectric barrier layers on the conductive layers.
4. The system as claimed in claim 1 , wherein the in-substrate portions of the bit lines comprise a dopant in the semiconductor substrate.
5. The system as claimed in claim 1 , wherein the buried word lines comprise floating gates therein.
6. An integrated circuit system, comprising:
a semiconductor substrate;
a first address line, further comprising:
a charge-trapping dielectric layer vertically on sidewalls of a trench in the semiconductor substrate,
a conductive layer on the dielectric layer, and
a barrier dielectric over the conductive layer;
second address lines perpendicular to the first address line and partially in the semiconductor substrate to form dual bit locations; and
conductive channels between the second address lines that are adjacent to the charge-trapping dielectric layer.
7. The system as claimed in claim 6 , further comprising:
first and second additional address lines parallel to the first address line operable therewith to form a plurality of dual bit locations.
8. The system as claimed in claim 6 , wherein the first address line further comprises a further barrier layer under the conductive layer.
9. The system as claimed in claim 6 , wherein the second address lines each further comprise an in-substrate portion in the semiconductor substrate and an above-substrate portion on the semiconductor substrate in a dielectric layer.
10. The system as claimed in claim 6 , further comprising a floating gate on the charge-trapping dielectric layer.