IP Library Patent Application 11552856
Patent Application
App. No. 11/552,856

Mounting Spring Elements on Semiconductor Devices, and Wafer-Level Testing Methodology

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Quick Facts
Patent No.
US None
App. No.
11/552,856
Abstract

Resilient contact structures are mounted directly to bond pads on semiconductor dies, prior to the dies being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies to be exercised (e.g., tested and/or burned-in) by connecting to the semiconductor dies with a circuit board or the like having a plurality of terminals disposed on a surface thereof. Subsequently, the semiconductor dies may be singulated from the semiconductor wafer, whereupon the same resilient contact structures can be used to effect interconnections between the semiconductor dies and other electronic components (such as wiring substrates, semiconductor packages, etc.). Using the all-metallic composite interconnection elements of the present invention as the resilient contact structures, burn-in can be performed at temperatures of at least 150° C., and can be completed in less than 60 minutes.

Claims (10)

1 - 46 . (canceled)

47 . An apparatus comprising:

a semiconductor wafer comprising a plurality of unsingulated semiconductor devices on said wafer, said semiconductor devices comprising a plurality of resilient contact structures mounted thereon;

a test board comprising a plurality of contact elements, said test board disposed in proximity to said semiconductor wafer, forming pressure connections between ones of said resilient contact structures and corresponding contact elements of said test board; and

means for exercising at least one of said semiconductor devices.

48 . The apparatus of claim 47 further comprising means for elevating a temperature of said at least one semiconductor device while exercising said at least one semiconductor device.

49 . The apparatus of claim 48 , wherein said means for elevating is capable of elevating said temperature of said at least one semiconductor devices to least 125° C.

50 . The apparatus of claim 47 , wherein said means for exercising exercises said at least one semiconductor device by providing electrical signals through said contact elements of said test board to said ones of said resilient contact structures.

51 . The apparatus of claim 50 further comprising means for monitoring a response of said at least one semiconductor device to said electrical signals.

52 . The apparatus of claim 51 further comprising means for evaluating said response.

Assignments (2)
RELEASE OF SECURITY INTEREST Recorded Aug 7, 2025
From: HSBC BANK USA, NATIONAL ASSOCIATION
To: FORMFACTOR, INC.
Reel/Frame 072853/0001 →
SECURITY INTEREST IN UNITED STATES PATENTS AND TRADEMARKS Recorded Jul 12, 2016
From: FORMFACTOR, INC.; ASTRIA SEMICONDUCTOR HOLDINGS, INC.; CASCADE MICROTECH, INC.; MICRO-PROBE INCORPORATED
To: HSBC BANK USA, NATIONAL ASSOCIATION
Reel/Frame 039184/0280 →