Integrated circuit testing module including signal shaping interface

1. A system to test an integrated circuit, comprising:

one or more input components configured to receive input signals having a first slew rate and to output information derived from the input signals;

one or more data generating components coupled to receive the information from the one or more input components and configured to generate test signals responsive to the information; and

one or more output components coupled to the data generating components and configured to convey the generated test signals to the integrated circuit at a second slew rate, the one or more output components being coupled to the integrated circuit in a detachable configuration, the second slew rate being faster than the first slew rate.

2. The system of claim 1 , further including a command generating component coupled to the one or more input components.

3. The system of claim 2 , wherein the command generating component is configured to generate a command responsive to a test plan.

4. The system of claim 1 , wherein the one or more data generating components are further configured to generate the test signals responsive to an address.

5. The system of claim 1 , further including an address generating component coupled to the one or more data generating components.

6. The system of claim 5 , wherein the address generating component and the one or more data generating components are detachable from the automated testing equipment.

7. The system of claim 1 , further including a clock adjustment component coupled to the one or more input components and configured to generate an adjustment between a clock signal sent to the integrated circuit and a clock signal used to determine when to expect data from the integrated circuit.

8. The system of claim 7 , wherein the adjustment is responsive to the signals received from the automated testing equipment.

9. The system of claim 1 , further comprising a test plan memory component coupled to the one or more input components and configured to store at least one test plan, the one or more data generating components further configured to generate test signals responsive to the one or more test plans.

10. The system of claim 9 , wherein the test plan memory component is detachable from the one or more data generating components.

11. The system of claim 1 , wherein the one or more input components are configured to receive the signals from the automated testing equipment at a first clock frequency, and the one or more output components are configured to convey the generated test signals to the integrated circuit at a second clock frequency higher than the first clock frequency.

12. The system of claim 11 , further comprising one or more data receiving components configured to receive data from the integrated circuit at the second clock frequency and to communicate to the automated testing equipment in response to the received data at the first clock frequency.

13. The system of claim 11 , wherein the one or more data receiving components are configured to compress the received data using a test plan.

14. The system of claim 11 , wherein the one or more data receiving components are configured to compare the received data to an expected result responsive to a test plan.

15. The system of claim 1 , wherein the one or more input components and the one or more output components are included in a test module, the test module being one of a plurality of test modules included in a test array configured to test a plurality of integrated circuits, the test array including a memory configured to store one or more test plans for testing the plurality of integrated circuits, the memory being shared by the plurality of test modules.

16. The system of claim 1 , wherein the integrated circuit is a memory device.

17. The system of claim 1 , further including the integrated circuit.

18. The system of claim 1 , wherein receiving the information from the one or more input components at the data generating components comprises receiving addresses and test data; and

wherein generating the test signals responsive to the information comprises using the addresses and test data to generate additional addresses and test data to be included in the test signals.

19. A method performed by a test module, comprising:

receiving signals having a first slew rate from an automated testing equipment;

generating test signals within the test module responsive to the signals received from the automated testing equipment; and

sending the generated test signals to an integrated circuit at a second slew rate faster than the first slew rate.

20. The method of claim 19 , wherein the signals received from the automated testing equipment include a signal to generate an adjustment between a clock signal sent to the integrated circuit and a clock signal used to determine when to expect data from the integrated circuit.

21. The method of claim 19 , wherein the signals received from the automated testing equipment include a signal to select at least one test plan, used to generate the test signals to be sent to the integrated circuit, from a test plan memory component including the at least one test plan.

22. The method of claim 21 , wherein the test plan memory component is detachable from the test module.

23. The method of claim 19 , further comprising

receiving the signals from the automated testing equipment at the test module at a first clock frequency, and

sending the generated test signals to the integrated circuit at a second clock frequency higher than the first clock frequency.

24. The method of claim 23 , further comprising

receiving signals from the integrated circuit at the second clock frequency, the received signals being responsive to the test signals sent to the integrated circuit, and

sending a communication from the test module to the automated testing equipment in response to the signals received from the integrated circuit.

25. The method of claim 19 , further comprising detaching the test module from the integrated circuit, and attaching a second integrated circuit to the test module to test the second integrated circuit.

26. An integrated circuit tested using the method of claim 19 .

27. A system comprising:

means for receiving signals having a first slew rate from an automated testing equipment at a test module;

means for generating test signals within the test module responsive to the signals received from the automated testing equipment; and

means for sending the generated test signals to an integrated circuit to be tested at a second slew rate faster than the first slew rate.