Integrated passive device system

1. A method of manufacturing an integrated passive device system comprising:

forming a first dielectric layer in direct contact with a semiconductor substrate;

depositing a metal capacitor layer having a first segment and a second segment, each segment in direct contact with the first dielectric layer;

depositing a silicide layer having a first portion and a second portion over the first dielectric layer and the metal capacitor layer, wherein:

the first portion is in direct contact with the first dielectric layer between the first segment and the second segment, and

the second portion is in direct contact with the second segment and the first dielectric layer, the second portion completely covering the second segment;

forming a second dielectric layer having a first section and a second section over the metal capacitor layer, wherein:

the first section is in direct contact with the first portion, the first section partially covering the first portion, and

the second section is in direct contact with the second portion and the first dielectric layer, the second section partially covering the second portion;

depositing a conductive layer over the second dielectric layer including:

forming a top plate from the conductive layer for forming an integrated capacitor,

forming a terminal for the integrated capacitor,

forming a contact for an integrated resistor,

forming a bridge for an integrated inductor, and

forming an analog circuit by interconnecting the integrated capacitor, the integrated resistor, and the integrated inductor;

applying a barrier layer over the conductive layer; and

depositing a copper layer over the barrier layer.

2. The method as claimed in claim 1 further comprising depositing an insulation layer over the conductive layer.

3. The method as claimed in claim 1 further comprising forming a contact on the integrated capacitor includes:

applying an insulation layer over the conductive layer;

forming an interconnect via in the insulation layer for exposing the conductive layer; and

forming a system interconnect coupled to the conductive layer.

4. A method of manufacturing an integrated passive device system comprising:

forming a first dielectric layer in direct contact with a semiconductor substrate, the first dielectric layer includes a silicon dioxide layer;

depositing a metal capacitor layer having a first segment and a second segment, each segment in direct contact with the first dielectric layer, the metal capacitor layer includes a first plate of an integrated capacitor;

depositing a silicide layer having a first portion and a second portion over the first dielectric layer and the metal capacitor layer, wherein:

the first portion is in direct contact with the first dielectric layer between the first segment and the second segment, and

the second portion is in direct contact with the second segment and the first dielectric layer, the second portion completely covering the second segment;

forming a second dielectric layer having a first section and a second section over the metal capacitor layer, wherein:

the first section is in direct contact with the firs portion, the first section partially covering the first portion, and

the second section is in direct contact with the second portion and the first dielectric layer, the second section partially covering the second portion;

depositing a conductive layer over the second dielectric layer including:

forming a top plate from the conductive layer for forming an integrated capacitor,

forming a terminal for the integrated capacitor,

forming a contact for an integrated resistor,

forming a bridge for an integrated inductor, and

forming an analog circuit by interconnecting the integrated capacitor, the integrated resistor, and the integrated inductor;

applying a barrier layer over the conductive layer; and

depositing a copper layer over the barrier layer.

5. The method as claimed in claim 4 further comprising:

depositing the second dielectric includes depositing the second dielectric layer over the silicide layer.

6. The method as claimed in claim 4 wherein depositing the conductive layer includes forming a body of the integrated inductor and contacts of both the integrated resistor and the integrated capacitor with the conductive layer.

7. The method as claimed in claim 4 further comprising depositing an insulation layer over the conductive layer by spin-coating a polyimide layer.

8. The method as claimed in claim 4 further comprising forming a contact on the integrated capacitor includes:

applying an insulation layer over the conductive layer includes spin-coating a polymer layer;

forming an interconnect via in the insulation layer for exposing the conductive layer includes exposing the conductive layer or the metal capacitor layer; and

forming a system interconnect includes coupling a solder ball, a solder column, a stud bump, or a bond wire coupled to the conductive layer.

9. An integrated passive device system comprising:

a semiconductor substrate;

a first dielectric layer in direct contact with the semiconductor substrate;

a metal capacitor layer having a first segment and a second segment, wherein each segment is in direct contact with the first dielectric layer;

a silicide layer having a first portion and second portion over the first dielectric layer and the metal capacitor layer, wherein:

the first portion is in direct contact with the first dielectric layer between the first segment and the second segment, and

the second portion is in direct contact with the second segment and the first dielectric layer, the second portion completely covering the second segment;

a second dielectric layer having a first section and a second section over the metal capacitor layer, wherein;

the first section is in direct contact with the first portion, the first section partially covering the first portion, and

the second section is in direct contact with the second portion and the first dielectric layer, the second section partially covering the second portion;

a conductive layer over the second dielectric layer including:

a top plate from the conductive layer for forming an integrated capacitor,

a terminal from the conductive layer for the integrated capacitor,

a contact from the conductive layer for an integrated resistor,

a bridge from the conductive layer for an integrated inductor, and

an analog circuit by interconnecting the integrated capacitor, the integrated resistor, and the integrated inductor with the conductive layer;

a barrier layer over the conductive layer; and

a copper layer over the barrier layer.

10. The system as claimed in claim 9 further comprising an insulation layer over the conductive layer.

11. The system as claimed in claim 9 further comprising a contact on the integrated capacitor includes:

an insulation layer over the conductive layer;

an interconnect via formed in the insulation layer for exposing the conductive layer; and

a system interconnect coupled to the conductive layer.

12. The system as claimed in claim 9 wherein the first dielectric layer is a silicon dioxide layer.

13. The system as claimed in claim 12 wherein the conductive layer includes a body of the integrated inductor and contacts of both the integrated resistor and the integrated capacitor.

14. The system as claimed in claim 12 further comprising an insulation layer over the conductive layer includes a polyimide layer.

15. The system as claimed in claim 12 further comprising a contact on the integrated capacitor includes:

an insulation layer over the conductive layer includes a polymer;

an interconnect via in the insulation layer for exposing the conductive layer includes the conductive layer or the metal capacitor layer exposed; and

a system interconnect including a solder ball, a solder column, a stud bump, or a bond wire coupled to the conductive layer.