Memory device
The present invention provides a memory device of a type that outputs a ready signal to the outside, and that is capable of achieving an enhanced data transfer rate and a uniform latency time. A memory device according to the present invention includes a ready signal sending portion, and the ready signal sending portion monitors a memory portion to detect the memory portion becoming ready for reading or writing of specified data. The ready signal sending portion generates a first ready signal that changes from a busy state to a ready state after the detection and an enabling signal that changes from a disable state to an enable state on the basis of a preset ready generating timing value. When the first ready signal is in the ready state and the enabling signal is in the enable state, the ready signal sending portion sends to the outside a second ready signal that is in a ready state.
1. A memory device that receives from outside a command about reading, writing, or erasing of specified data, and that sends a ready signal to the outside when said specified data has become ready for reading on the basis of said command, or when an operation of writing or erasing said specified data has ended on the basis of said command, said memory device comprising:
a memory portion that is capable of any of reading, writing, and erasing of said specified data; and
a ready signal sending portion that sends said ready signal to the outside when a first condition and a second condition are both satisfied, where said first condition is satisfied when a state in which said specified data is ready for reading from said memory portion is detected, or when an end of the operation of writing or erasing said specified data to or from said memory portion is detected, and said second condition is satisfied when a preset ready generating timing is satisfied, and
said ready signal sending portion monitors said memory portion to detect the state in which said specified data is ready for reading from said memory portion, or to detect the end of the operation of writing or erasing said specified data to or from said memory portion, and said ready signal sending portion generates a first ready signal that changes from a busy state to a ready state after the detection, and an enabling signal that changes from a disable state to an enable state on the basis of a preset value of the ready generating timing, and said ready signal sending portion sends a second ready signal in a ready state to the outside when said first ready signal is in the ready state and said enabling signal is in the enable state.
2. The memory device according to claim 1 ,
wherein said ready signal sending portion comprises:
a first ready signal generating portion that generates said first ready signal;
a ready generating timing value setting portion that is capable of setting said ready generating timing value;
an enabling signal generating portion that generates said enabling signal that goes into said disable state when said command about reading, writing, or erasing is inputted, and that goes into said enable state according to a timing based on said ready generating timing value; and
a second ready signal generating portion that receives said first ready signal and said enabling signal to generate said second ready signal.
3. The memory device according to claim 2 ,
wherein said memory portion comprises an area where original information about said ready generating timing value is stored, and
when a given command sent from outside is received, said ready generating timing value is set in said ready generating timing value setting portion on the basis of said original information.
4. The memory device according to claim 2 ,
wherein said ready generating timing value setting portion is capable of changing said ready generating timing value in setting state, and
said ready generating timing value is changed on the basis of an operation applied from outside.