Scalar result producing method in vector/scalar system by vector unit from vector results according to modifier in vector instruction
View Patent ↗Described herein is a method and system for executing instructions. The system comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector unit for executing vector instructions each defining multiple value pairs; and an instruction decoder for receiving a single stream of instructions including scalar instructions and vector instructions and operable to direct scalar instructions to the scalar unit and vector instructions to the vector unit. The vector unit can comprises a plurality of value processing units and a scalar result unit. The scalar unit can comprise a scalar register file. Communication between the vector unit and the scalar unit is enabled by allowing the vector unit to access the scalar register file and allowing the scalar unit to access output from the scalar result unit. The output of the scalar result unit may be based on the relative magnitudes of outputs from the plurality of value processing units.
1. A method for instruction execution comprising:
receiving a scalar instruction and a vector instruction, wherein the scalar instruction identifies a pair of values and the vector instruction includes a modifier and identifies multiple value pairs;
executing the scalar instruction in a scalar unit;
executing the vector instruction in a vector unit, wherein the vector unit comprises a plurality of processing units each operable to process one of said multiple value pairs, thereby generating a plurality of parallel results; and
generating a scalar result in a scalar result unit based on the plurality of parallel results, wherein the generation of the scalar result is based on the modifier.
2. The method of claim 1 , wherein the multiple value pairs are based on at least one value stored in a scalar register file.
3. The method of claim 1 , wherein the vector unit comprises a vector register file holding one or more operands addressable by said vector instruction for supply to the plurality of processing units.
4. The method of claim 1 , wherein each value pair in the multiple value pairs comprises a first packed operand and a second packed operand.
5. The method of claim 1 , wherein the scalar instruction comprises an address of a storage location for a result.
6. The method of claim 1 , wherein the vector instruction comprises an address of a storage location for the plurality of parallel results.
7. The method of claim 1 , wherein the vector instruction comprises an address of a storage location for the scalar result generated by the scalar result unit.
8. The method of claim 1 , wherein the vector instruction further comprises an immediate value, and wherein the multiple value pairs are based on the immediate value.
9. The method of claim 1 , wherein the plurality of processing units performs an operation on an image comprising a plurality of pixel values.
10. The method of claim 1 , wherein the method further comprises holding a program in the form of instructions in a common instruction space.
11. The method of claim 1 , wherein the method further comprises holding data values in a data memory.
12. The method of claim 1 , wherein the scalar instruction is encoded optionally in 16-bit, 32-bit and 48-bit forms.
13. The method of claim 1 , wherein the vector instruction is encoded optionally in 48 and 80-bit forms.
14. The method of claim 1 , wherein the vector instruction and the scalar instruction each include a bit sequence at predetermined bit locations, said bit sequence being detectable by an instruction decoder to identify an instruction as a scalar type or a vector type.
15. The method of claim 14 , wherein the bit sequence in vector instructions is all zeros.
16. The method of claim 1 , wherein the scalar result is one result from the plurality of parallel results.
17. The method of claim 1 , wherein the scalar result unit further generates a sum of the plurality of parallel results.
18. The method of claim 1 , wherein the scalar result is an index of a maximum value in the plurality of parallel results.
19. The method of claim 1 , wherein the scalar result is an index of a minimum value in the plurality of parallel results.
20. The method of claim 1 , wherein the scalar result is a maximum value in the plurality of parallel results.
21. The method of claim 1 , wherein the scalar result is a minimum value in the plurality of parallel results.
22. A system for instruction execution comprising:
a first memory for holding a scalar instruction and a vector instruction;
a second memory;
a first circuit for receiving the scalar instruction and the vector instruction;
a second circuit for processing one or more values, from the second memory, according to the scalar instruction;
a third circuit for processing a plurality of value pairs, from the second memory, according to the vector instruction, wherein the third circuit comprises a plurality of processing units each operable to process a single value pair in the plurality of value pairs, thereby generating a plurality of vector results; and
a fourth circuit for generating a scalar result based on the plurality of vector results, wherein the scalar result is generated according to a modifier in the vector instruction.
23. The system of claim 22 , wherein the scalar result is the sum of the plurality of vector results.
24. The system of claim 22 , wherein the scalar result is an index of a maximum value in the plurality of vector results.
25. The system of claim 22 , wherein the scalar result is an index of a minimum value in the plurality of vector results.
26. The system of claim 22 , wherein the scalar result is a maximum value in the plurality of vector results.
27. The system of claim 22 , wherein the scalar result is a minimum value in the plurality of vector results.
28. The system of claim 22 , wherein the scalar result is an index of a maximum value in the set of parallel results.
29. The system of claim 22 , wherein the scalar result is an index of a minimum value in the set of parallel results.